Structure Of The Can Core's Can Protocol Controller - Texas Instruments Concerto F28M36 Series Technical Reference Manual

CAN Bit Timing
It has to be considered that SJW may not be larger than the smaller of the phase buffer segments and
that the propagation time segment limits that part of the bit time that may be used for the phase buffer
segments.
The combination Prop_Seg = 1 and Phase_Seg1 = Phase_Seg2 = SJW = 4 allows the largest possible
oscillator tolerance of 1.58%. This combination with a Propagation Time Segment of only 10% of the bit
time is not suitable for short bit times; it can be used for bit rates of up to 125 kBit/s (bit time = 8 μs) with a
bus length of 40 m.
23.12.2 Configuration of the CAN Bit Timing
In the CAN, the bit timing configuration is programmed in two register bytes, additionally a third byte for a
baud rate prescaler extension of 4 bits (BRPE) is provided. The sum of Prop_Seg and Phase_Seg1 (as
TSEG1) is combined with Phase_Seg2 (as TSEG2) in one byte, SJW and BRP (plus BRPE in third byte)
are combined in the other byte (see
Figure 23-15. Structure of the CAN Core's CAN Protocol Controller
System clock
Receive_Data
Transmit_Data
In this bit timing register, the components TSEG1, TSEG2, SJW and BRP have to be programmed to a
numerical value that is one less than its functional value; so instead of values in the range of [1...n],
values in the range of [0...n-1] are programmed. That way, e.g. SJW (functional range of [1...4]) is
represented by only two bits.
Therefore the length of the Bit time is (programmed values) [TSEG1 + TSEG2 + 3] t
[Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] t
The data in the Bit Timing register is the configuration input of the CAN protocol controller. The baud rate
prescaler (configured by BRPE/BRP) defines the length of the time quantum (the basic time unit of the bit
time); the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number of time quanta in
the bit time.
The processing of the bit time, the calculation of the position of the Sample Point, and occasional
synchronizations are controlled by the Bit timing state machine, which is evaluated once each time
quantum. The rest of the CAN protocol controller, the Bit Stream Processor (BSP) state machine, is
evaluated once each bit time, at the Sample Point.
The Shift register serializes the messages to be sent and parallelizes received messages. Its loading and
shifting is controlled by the BSP.
1572
M3 Controller Area Network (CAN)
Figure 23-15).
Configuration (BRPE/BRP)
Scaled_Clock (tq)
Baudrate_
prescaler
Bit
timing
logic
Next_Data_Bit
Configuration (TSEG1, TSEG2, SJW)
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Sample_Point
Sampled_Bit
Sync_Mode
Bit_to_send
Bus-Off
Control
Shift-Register
.
q
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Control
Status
Received_Data_Bit
Send_Message
Received_Message
or (functional values)
q
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