M3 To C28 Core Flag (Mtocipcflg) Register; M3 To C28 Core Flag (Mtocipcflg) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 1-177. M3 to C28 IPC Clear (MTOCIPCCLR) Register Field Descriptions (continued)
Bit
Field
3
IPC4
2
IPC3
1
IPC2
0
IPC1

1.13.11.3 M3 to C28 Core Flag (MTOCIPCFLG) Register

31
30
IPC32
IPC31
R-0
R-0
23
22
IPC24
IPC23
R-0
R-0
15
14
IPC16
IPC15
R-0
R-0
7
6
IPC8
IPC7
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-178. M3 to C28 Core Flag (MTOCIPCFLG) Register Field Descriptions
Bit
Field
31
IPC32
30
IPC31
29
IPC30
28
IPC29
27
IPC28
26
IPC27
25
IPC26
SPRUHE8E – October 2012 – Revised November 2019
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Value
Description
0
MTOCIPCCLR Interrupt 4. M3 to C28 IPC interrupt 4 request clear. If this bit is cleared by writing a
'1' then MTOCINT1 is raised to the C28 PIE. The status of this bit is not readable in this register – it
is readable in the corresponding bit in the MTOCIPCFLG and STS registers.
0
MTOCIPCCLR Interrupt 3. M3 to C28 IPC interrupt 3 request clear. If this bit is cleared by writing a
'1' then MTOCINT1 is raised to the C28 PIE. The status of this bit is not readable in this register – it
is readable in the corresponding bit in the MTOCIPCFLG and STS registers.
0
MTOCIPCCLR Interrupt 2. M3 to C28 IPC interrupt 2 request clear. If this bit is cleared by writing a
'1' then MTOCINT1 is raised to the C28 PIE. The status of this bit is not readable in this register – it
is readable in the corresponding bit in the MTOCIPCFLG and STS registers.
0
MTOCIPCCLR Interrupt 1. M3 to C28 IPC interrupt 1 request clear. If this bit is cleared by writing a
'1' then MTOCINT1 is raised to the C28 PIE. The status of this bit is not readable in this register – it
is readable in the corresponding bit in the MTOCIPCFLG and STS registers..
Figure 1-166. M3 to C28 Core Flag (MTOCIPCFLG) Register
29
28
IPC30
IPC29
R-0
R-0
21
20
IPC22
IPC21
R-0
R-0
13
12
IPC14
IPC13
R-0
R-0
5
4
IPC6
IPC5
R-0
R-0
Value
Description
0
MTOCIPCFLG Flag 32. M3 to C28 core IPC flag 32 status. The bit is '1' if the corresponding
MTOCIPCSET bit has been written with a '1' and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a '1."
0
MTOCIPCFLG Flag 31. M3 to C28 core IPC flag 31 status. The bit is '1' if the corresponding
MTOCIPCSET bit has been written with a '1' and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a '1."
0
MTOCIPCFLG Flag 30. M3 to C28 core IPC flag 30 status. The bit is '1' if the corresponding
MTOCIPCSET bit has been written with a '1' and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a '1."
0
MTOCIPCFLG Flag 29. M3 to C28 core IPC flag 29 status. The bit is '1' if the corresponding
MTOCIPCSET bit has been written with a '1' and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a '1."
0
MTOCIPCFLG Flag 28. M3 to C28 core IPC flag 28 status. The bit is '1' if the corresponding
MTOCIPCSET bit has been written with a '1' and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a '1."
0
MTOCIPCFLG Flag 27. M3 to C28 core IPC flag 27 status. The bit is '1' if the corresponding
MTOCIPCSET bit has been written with a '1' and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a '1."
0
MTOCIPCFLG Flag 26..M3 to C28 core IPC flag 26 status. The bit is '1' if the corresponding
MTOCIPCSET bit has been written with a '1' and MTOCIPCCLR or MTOCIPCACK bit has not been
written with a '1."
Copyright © 2012–2019, Texas Instruments Incorporated
27
26
IPC28
IPC27
R-0
R-0
19
18
IPC20
IPC19
R-0
R-0
11
10
IPC12
IPC11
R-0
R-0
3
2
IPC4
IPC3
R-0
R-0
System Control and Interrupts
System Control Registers
25
24
IPC26
IPC25
R-0
R-0
17
16
IPC18
IPC17
R-0
R-0
9
8
IPC10
IPC9
R-0
R-0
1
0
IPC2
IPC1
R-0
R-0
281

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