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Memory Regions, Types and Attributes
The processor reserves regions of the Private peripheral bus (PPB) address range for core peripheral
registers (see the Cortex-M3 Peripherals chapter).
Note: Within the memory map, all reserved space returns a bus fault when read or written.
24.6 Memory Regions, Types and Attributes
The memory map and the programming of the MPU split the memory map into regions. Each region has a
defined memory type, and some regions have additional memory attributes. The memory type and
attributes determine the behavior of accesses to the region.
The memory types are:
•
Normal: The processor can re-order transactions for efficiency and perform speculative reads.
•
Device: The processor preserves transaction order relative to other transactions to Device or Strongly
Ordered memory.
•
Strongly Ordered: The processor preserves transaction order relative to all other transactions.
The different ordering requirements for Device and Strongly Ordered memory mean that the memory
system can buffer a write to Device memory but must not buffer a write to Strongly Ordered memory.
An additional memory attribute is Execute Never (XN), which means the processor prevents instruction
accesses. A fault exception is generated only on execution of an instruction executed from an XN region.
24.6.1 Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system does not
guarantee that the order in which the accesses complete matches the program order of the instructions,
providing the order does not affect the behavior of the instruction sequence. Normally, if correct program
execution depends on two memory accesses completing in program order, software must insert a memory
barrier instruction between the memory access instructions (see
However, the memory system does guarantee ordering of accesses to Device and Strongly Ordered
memory. For two memory access instructions A1 and A2, if both A1 and A2 are accesses to either Device
or Strongly Ordered memory, and if A1 occurs before A2 in program order, A1 is always observed before
A2.
24.6.2 Behavior of Memory Accesses
Table 24-13
shows the behavior of accesses to each region in the memory map. See
more information on memory types and the XN attribute. Concerto™ devices may have reserved memory
areas within the address ranges shown below.
Address Range
0x0000.0000 - 0x1FFF.FFFF Code
0x2000.0000 - 0x3FFF.FFFF SRAM
0x4000.0000 - 0x5FFF.FFFF Peripheral
0x6000.0000 - 0x9FFF.FFFF External RAM
0xA000.0000 -
0xDFFF.FFFF
0xE000.0000- 0xE00F.FFFF
0xE010.0000- 0xFFFF.FFFF Reserved
1616
Cortex-M3 Processor
Table 24-13. Memory Access Behavior
Memory Region
Memory Type
Normal
Normal
Device
Normal
External device
Device
Private peripheral
Strongly Ordered
bus
-
Copyright © 2012–2019, Texas Instruments Incorporated
Section
24.6.3).
Execute Never
(XN)
This executable region is for program
code. Data can also be stored here.
-
Includes Boot ROM and Flash on
Concerto devices.
This executable region is for data.
Code can also be stored here. This
-
region includes bit band and bit band
alias areas (see
This region includes bit band and bit
XN
band alias areas (see
-
This executable region is for data.
This region is for external device
XN
memory.
This region includes the NVIC, system
XN
timer, and system control block.
-
-
SPRUHE8E – October 2012 – Revised November 2019
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Section 24.6
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Description
Table
24-14).
Table
24-15).
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