Ethernet Mac Interrupt Mask (Macim) Register - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Ethernet MAC Register Descriptions
Table 19-3. Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Register Field
Bit Field
4 RXER
3 FOV
2 TXEMP
1 TXER
0 RXINT
19.6.2 Ethernet MAC Interrupt Mask (MACIM) Register, offset 0x004
The Ethernet MAC Interrupt Mask (MACIM) register is shown and described in the figure and table below.
31
15 14
7 6
Reserved PHYINTM
R-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
1426
M3 Ethernet Media Access Controller (EMAC)
Descriptions (continued)
Value Description
Receive Error
0 No interrupt
1 An error was encountered on the receiver. The possible errors that can cause this interrupt bit to be
set are: 1
• A receive error occurs during the reception of a frame (100 Mbps only).
• The frame is not an integer number of bytes (dribble bits) due to an alignment error.
• The CRC of the frame does not pass the FCS check.
• The length/type field is inconsistent with the frame data size when interpreted as a length field.
This bit is cleared by writing a 1 to it.
FIFO Overrun
0 No interrupt
1 An overrun was encountered on the receive FIFO.
Transmit FIFO Empty
0 No interrupt
1 The packet was transmitted and that the TX FIFO is empty.
This bit is cleared by writing a 1 to it.
Transmit Error
0 No interrupt
1 An error was encountered on the transmitter. The possible errors that can cause this interrupt bit to
be set are: 1
• The data length field stored in the TX FIFO exceeds 2032 decimal (buffer length - 16 bytes of
header data). The frame is not sent when this error occurs.
• The retransmission attempts during the backoff process have exceeded the maximum limit of 16
decimal.
Writing a 1 to this bit clears it and resets the TX FIFO write pointer.
Packet Received
0 No interrupt.
1 At least one packet has been received and is stored in the receiver FIFO
This bit is cleared by writing a 1 to it.
Figure 19-5. Ethernet MAC Interrupt Mask (MACIM) Register
13 12
5 4
MDINTM RXERM
R/W-1 R/W-1
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
11 10
Reserved
R-0
3 2
FOVM TXEMPM
R/W-1 R/W-1
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
16
9 8
1 0
TXERM RXINTM
R/W-1C R/W-1
Submit Documentation Feedback