Table of Contents
Advertisement
www.ti.com
31
30
GPIO95
R/W-0
23
22
GPIO91
R/W-0
15
14
GPIO87
R/W-0
7
6
GPIO83
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-56. GPIO Port C MUX 2 (GPCMUX2) Register Field Descriptions
Bit
Field
31-30
GPIO95
29-28
GPIO94
27-26
GPIO93
25-24
GPIO92
23-22
GPIO91
21-20
GPIO90
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
Figure 4-47. GPIO Port C MUX 2 (GPCMUX2) Register
29
28
GPIO94
R/W-0
21
20
GPIO90
R/W-0
13
12
GPIO86
R/W-0
5
4
GPIO82
R/W-0
Value
Description
Configure this pin as:
00
GPIO 95 - general purpose I/O 95 GPIO (default)
01
Reserved
10
MFSXA
11
Reserved
Configure this pin as:
00
GPIO 94 - general purpose I/O 94 GPIO (default)
01
Reserved
10
MCLKXA
11
Reserved
Configure this pin as:
00
GPIO 93 - general purpose I/O 93 GPIO (default)
01
Reserved
10
MDRA
11
Reserved
Configure this pin as:
00
GPIO 92 - general purpose I/O 92 GPIO (default)
01
Reserved
10
MDXA
11
Reserved
Configure this pin as:
00
GPIO 91- general purpose I/O 91 GPIO (default)
01
Reserved
10
Reserved
11
Reserved
Configure this pin as:
00
GPIO 90 - general purpose I/O 90 GPIO (default)
01
Reserved
10
Reserved
11
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
C28 General-Purpose Input/Output (GPIO)
27
26
GPIO93
R/W-0
19
18
GPIO89
R/W-0
11
10
GPIO85
R/W-0
3
2
GPIO81
R/W-0
General-Purpose Input/Output (GPIO)
25
24
GPIO92
R/W-0
17
16
GPIO88
R/W-0
9
8
GPIO84
R/W-0
1
0
GPIO80
R/W-0
413
Advertisement
Chapters
Table of Contents
