Timer Daisy Chain - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Prescale
11111101
11111110
11111111
2.3.2.1.1 Wait-for-Trigger Mode
The wait-for-trigger mode allows daisy chaining of the timer modules such that once configured, a single
timer can initiate mulitple timing events using the Timer triggers. Wait-for-trigger mode is enabled by
setting the TnWOT bit in the GPTMTnMR register. When the TnWOT bit is set, Timer N+1 does not begin
counting until the timer in the previous position in the daisy chain (Timer N) reaches its time-out event.
The daisy chain is configured such that GPTM1 always follows GPTM0, GPTM2 follows GPTM1, and so
on. If Timer A is in 32-bit mode (controlled by the GPTMCFG bit in the GPTMCFG register), it triggers
Timer A in the next module. If Timer A is in 16-bit mode, it triggers Timer B in the same module, and
Timer B triggers Timer A in the next module. Care must be taken that the TAWOT bit is never set in
GPTM0. Figure 2-2
one-shot and periodic modes.
2.3.2.2 Real-Time Clock Timer Mode
In real-time clock (RTC) mode, the concatenated versions of the Timer A and Timer B registers are
configured as an up-counter. When RTC mode is selected for the first time after reset, the counter is
loaded with a value of 0x1. All subsequent load values must be written to the GPTM Timer A Interval Load
(GPTMTAILR) register.
The input clock on an even CCP input is required to be 32.768 KHz in RTC mode. The clock signal is then
divided down to a 1-Hz rate and is passed along to the input of the counter.
When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from its
preloaded value of 0x1. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, the GPTM asserts the RTCRIS bit in GPTMRIS and continues counting until
either a hardware reset, or it is disabled by software (clearing the TAEN bit). When the timer value
reaches the terminal count, the timer rolls over and continues counting up from 0x0. If the RTC interrupt is
enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and generates a controller
interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR.
In addition to generating interrupts, a µMA trigger can be generated. The µDMA trigger is enabled by
configuring and enabling the appropriate µDMA channel. See Channel Configuration in the Micro Direct
Memory Access (µDMA) chapter.
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the
RTCEN bit is set in GPTMCTL.
SPRUHE8E – October 2012 – Revised November 2019
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Table 2-3. 16-Bit Timer With Prescaler Configurations (continued)
#Clock (Tc)
254
255
256
shows how the GPTMCFG bit affects the daisy chain. This function is valid for both
Figure 2-2. Timer Daisy Chain
GP Timer N+1
1 0
GP Timer N
1 0
Copyright © 2012–2019, Texas Instruments Incorporated
Max Time
166.4614
167.1168
167.7722
GPTMCFG
Timer B Timer BADCTrigger
Timer AADCTrigger
Timer A
GPTMCFG
Timer B Timer BADCTrigger
Timer A Timer AADCTrigger
Functional Description
Units
mS
mS
mS
M3 General-Purpose Timers
309