Set The Transmit Dxena Mode; Set The Transmit Interrupt Mode; Register Bit Used To Set The Transmit Dxena (Dx Delay Enabler) Mode; Register Bits Used To Set The Transmit Interrupt Mode - Texas Instruments Concerto F28M36 Series Technical Reference Manual

www.ti.com

15.9.13 Set the Transmit DXENA Mode

Table 15-60. Register Bit Used to Set the Transmit DXENA (DX Delay Enabler) Mode
Register Bit
SPCR1 7
15.9.13.1 DXENA Mode
The DXENA bit controls the delay enabler on the DX pin. Set DXENA to enable an extra delay for turn-on
time. This bit does not control the data itself, so only the first bit is delayed.
If you tie together the DX pins of multiple McBSPs, make sure DXENA = 1 to avoid having more than one
McBSP transmit on the data line at one time.

15.9.14 Set the Transmit Interrupt Mode

The transmitter interrupt (XINT) signals the CPU of changes to the serial port status. Four options exist for
configuring this interrupt. The options are set by the transmit interrupt mode bits, XINTM, in SPCR2.
Table 15-61. Register Bits Used to Set the Transmit Interrupt Mode
Register Bit
SPCR2 5-4
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
Name Function
DXENA DX delay enabler mode
DXENA = 0
DXENA = 1
Name Function
XINTM Transmit interrupt mode
XINTM = 00 XINT generated when XRDY changes from 0 to 1.
XINTM = 01 XINT generated by an end-of-block or end-of-frame
condition in a transmit multichannel selection mode. In
any of the transmit multichannel selection modes,
interrupt after every 16-channel block boundary has
been crossed within a frame and at the end of the frame.
For details, see
Between Block Transfers. In any other serial transfer
case, this setting is not applicable and, therefore, no
interrupts are generated.
XINTM = 10 XINT generated by a new transmit frame-
synchronization pulse. Interrupt on detection of each
transmit frame-synchronization pulse. This generates an
interrupt even when the transmitter is in its reset state.
This is done by synchronizing the incoming frame-
synchronization pulse to the CPU clock and sending it to
the CPU via XINT.
XINTM = 11 XINT generated when XSYNCERR is set. Interrupt on
frame-synchronization error. Regardless of the value of
XINTM, XSYNCERR can be read to detect this
condition. For more information on using XSYNCERR,
see
Synchronization Pulse.
Copyright © 2012–2019, Texas Instruments Incorporated
DX delay enabler is off.
DX delay enabler is on.
Section 15.6.7.3, Using Interrupts
Section 15.5.5, Unexpected Transmit Frame-
C28 Multichannel Buffered Serial Port (McBSP)
Transmitter Configuration
Reset
Type Value
R/W 0
Reset
Type Value
R/W 00
1145