Initialization Of A Transmit Object - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Module Initialization
NOTE: Writing to control registers in debug mode may influence the CAN state machine and further
message handling.
For debug support, the auto clear functionality of the following CAN registers is disabled:
• Error and Status register (clear of status flags by read)
• IF1 or IF2 Command registers (clear of DMAActive flag by r/w)
23.9 Module Initialization
After hardware reset, the Init bit in the CAN Control register is set and all CAN protocol functions are
disabled. The configuration of the bit timing and of the message objects should be completed before the
CAN protocol functions are enabled.
For the configuration of the message objects, see
For the configuration of the Bit Timing, see
The bits MsgVal, NewDat, IntPnd, and TxRqst of the message objects are reset to '0' by a hardware reset.
The configuration of a message object is done by programming Mask, Arbitration, Control and Data bits of
one of the IF1 or IF2 Interface register sets to the desired values. By writing the message object number
to bits [7:0] of the corresponding IF1 or IF2 Command register, the IF1 or IF2 Interface register content is
loaded into the addressed message object in the Message RAM.
The configuration of the bit timing requires that the CCE bit in the CAN Control register is set additionally
to Init. This is not required for the configuration of the message objects.
When the Init bit in the CAN Control register is cleared, the CAN Protocol Controller state machine of the
CAN Core and the message handler State Machine start to control the CAN's internal data flow. Received
messages which pass the acceptance filtering are stored into the Message RAM; messages with pending
transmission request are loaded into the CAN Core's Shift register and are transmitted via the CAN bus.
The CPU may enable the interrupt lines (setting IE0 and IE1 to '1') at the same time when it clears Init and
CCE. The status interrupts EIE and SIE may be enabled simultaneously.
CAN communication may be controlled in interrupt-driven or in polling mode. The Interrupt register points
to those message objects with IntPnd = '1'. It is updated even if the interrupt lines to the CPU are disabled
(IE0 or IE1 are zero).
The CPU may poll all MessageObject's NewDat and TxRqst bits in parallel from the NewData registers
and the Transmission Request registers. Polling can be made easier if all Transmit Objects are grouped at
the low numbers, all Receive Objects are grouped at the high numbers.
23.10 Configuration of Message Objects
The whole Message RAM should to be configured before the end of the initialization; however, it is also
possible to change the configuration of message objects during CAN communication.
23.10.1 Configuration of a Transmit Object for Data Frames
Figure 23-7 shows how a transmit object can be initialized.
MsgVal Arb Data
1 appl. appl.
• The arbitration bits (ID[28:0] and Xtd bit) are given by the application. They define the identifier and
type of the outgoing message. If an 11-bit Identifier (standard frame) is used (Xtd = '0'), it is
programmed to ID[28:18]. In this case, ID[17:0] can be ignored.
• The data registers (DLC[3:0] and Data0-7) are given by the application, TxRqst and RmtEn should not
be set before the data is valid.
• If the TxIE bit is set, the IntPnd bit will be set after a successful transmission of the message object.
• If the RmtEn bit is set, a matching received remote frame will cause the TxRqst bit to be set; the
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M3 Controller Area Network (CAN)
Section
Figure 23-7. Initialization of a Transmit Object
Mask EoB Dir
appl. 1 1
Copyright © 2012–2019, Texas Instruments Incorporated
Section 23.10.
23.12.2.
NewDat MsgLst RxIE
0 0 0
SPRUHE8E – October 2012 – Revised November 2019
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TxIE IntPnd RmtEn
appl. 0 appl.
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TxRqst
0