Examples Of I2C Master Timer Period Versus Speed Mode - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Functional Description
Table 22-1. Examples of I2C Master Timer Period versus Speed Mode
System Clock
4 MHz
6 MHz
12.5 MHz
16.7 MHz
20 MHz
25 MHz
33 MHz
40 MHz
50 MHz
80 MHz
22.3.3 Interrupts
The I2C module can generate interrupts when the following conditions are observed:
• Master transaction completed
• Master arbitration lost
• Master transaction error
• Slave transaction received
• Slave transaction requested
• Stop condition on bus detected
• Start condition on bus detected
The I2C master and I2C slave modules have separate interrupt signals. While both modules can generate
interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller.
22.3.3.1 I2C Master Interrupts
The I2C master module generates an interrupt when a transaction completes (either transmit or receive),
when arbitration is lost, or when an error occurs during a transaction. To enable the I2C master interrupt,
software must set the IM bit in the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt
condition is met, software must check the ERROR and ARBLST bits in the I2C Master Control/Status
(I2CMCS) register to verify that an error didn't occur during the last transaction and to ensure that
arbitration has not been lost. An error condition is asserted if the last transaction wasn't acknowledged by
the slave. If an error is not detected and the master has not lost arbitration, the application can proceed
with the transfer. The interrupt is cleared by writing a 1 to the IC bit in the I2C Master Interrupt Clear
(I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C
Master Raw Interrupt Status (I2CMRIS) register.
22.3.3.2 I2C Slave Interrupts
The slave module can generate an interrupt when data has been received or requested. This interrupt is
enabled by setting the DATAIM bit in the I2C Slave Interrupt Mask (I2CSIMR) register. Software
determines whether the module should write (transmit) or read (receive) data from the I2C Slave Data
(I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status (I2CSCSR)
register. If the slave module is in receive mode and the first byte of a transfer is received, the FBR bit is
set along with the RREQ bit. The interrupt is cleared by setting the DATAIC bit in the I2C Slave Interrupt
Clear (I2CSICR) register.
In addition, the slave module can generate an interrupt when a start and stop condition is detected. These
interrupts are enabled by setting the STARTIM and STOPIM bits of the I2C Slave Interrupt Mask
(I2CSIMR) register and cleared by writing a 1 to the STOPIC and STARTIC bits of the I2C Slave Interrupt
Clear (I2CSICR) register.
1526
M3 Inter-Integrated Circuit (I2C) Interface
Timer Period Standard Mode
0x01 100 Kbps
0x02 100 Kbps
0x06 89 Kbps
0x08 93 Kbps
0x09 100 Kbps
0x0C 96.2 Kbps
0x10 97.1 Kbps
0x13 100 Kbps
0x18 100 Kbps
0x27 100 Kbps
Copyright © 2012–2019, Texas Instruments Incorporated
Timer Period
-
-
0x01
0x02
0x02
0x03
0x04
0x04
0x06
0x09
SPRUHE8E – October 2012 – Revised November 2019
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Fast Mode
312 Kbps
278 Kbps
333 Kbps
312 Kbps
330 Kbps
400 Kbps
357 Kbps
400 Kbps