Low-Power Modes Configuration - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Low Power Modes
Mode C28 LPMCR0
register
Bits [1:0]
Normal X,X
IDLE 0,0
(3)
STANDBY ] 0,1
(1)
The Exit column lists which signals or under what conditions the low power mode will be exited. A low signal, on any of the
signals, will exit the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the
device. Otherwise the IDLE mode will not be exited and the device will go back into the indicated low power mode
(2)
If the control subsystem receives an XRS while in low power mode, it will reset the control subsystem.
(3)
In the device, the M3 CPU is the master. It is expected that when the M3 subsystem is in deep-sleep mode, the C28 subsystem
will also be in a low power mode. When the M3 subsystem is in deep-sleep mode, the C28 subsystem is not expected to be in
normal power mode. In other words, the M3 subsystem can enter deep-sleep only when the C28 subsystem is in STANDBY
mode.
(4)
The GPIO0.async to GPIO63.async are the asynchronous version of the input signal which come straight from the pin before
any qualification or synchronization inside GPIO. The qualification is done with the OSC clock inside the C28 LPM block
1.9.1.2.1 Entering Low-Power Mode
The system enters low-power mode upon execution of the IDLE instruction. The low-power mode bits
(LPM, [1:0]) of the CLPMCR0 register are only valid when the IDLE instruction is executed. The user must
set the LPM bits to the appropriate mode before executing the IDLE instruction.
Refer to the TMS320C28x DSP CPU and Instruction Set Reference Guide, SPRU430, which describes
the assembly language instructions of the TMS320C28x device.
1.9.1.2.1.1 IDLE Mode
If the CLPMCR0 bits [1:0] are set to (0, 0) and upon execution of an IDLE instruction, the processor stops
executing further and enters into IDLE mode. The LPM block performs no tasks during this mode until a
valid wakeup condition occurs.
1.9.1.2.1.2 Standby Mode
If the CLPMCR0 bits [1:0] are set to (0, 1) and upon execution of an IDLE instruction, the processor stops
executing further and enters into STANDBY mode. The LPM block performs no tasks during this mode
until a valid wakeup condition occurs. Refer to the Low-Power Modes Registers section of this document
for CLPMCR0 register details.
1.9.1.2.2 Wake UP From Low-Power Mode
1.9.1.2.2.1 Idle Mode
This mode is exited by any enabled C28 interrupt that is recognized by the processor or the C28NMIINT
(C28x Non-maskable interrupt).
1.9.1.2.2.2 Standby Mode
Any GPIO port signal (0 to 63) or MTOCIPCINT2 (interrupt from MTOC IPC peripheral) can wake the
device from STANDBY mode. To use the GPIO wakeup, the user must select which signal(s) will wake
the device in the GPIOLPMSELx register. The selected signal(s) are also qualified by the OSCCLK before
waking the control subsystem, depending on the QUALSTDBY bits (bits [7:2] of the CLPMCR0 register) .
Refer to the GPIOs chapter for more details on the GPIOLPMSELx registers.
144
System Control and Interrupts
Table 1-26. Low-Power Modes Configuration
OSCCLK CLKIN to C28
CPU
On On
On On
On Off
Copyright © 2012–2019, Texas Instruments Incorporated
CPUCLK SYSCLKOUT
On On
Off On
Off Off
SPRUHE8E – October 2012 – Revised November 2019
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(1)
Exit
-
(2)
XRSn ,
Any Enabled
C28
Interrupt,C28
NMI
(2)
XRSn
,GPIO0.async to
(4)
GPIO63.async
MTOCIPCINT2