Overview Of Parallel Gpio Bootloader Operation - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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6.6.15.7 C-Boot ROM Parallel Boot Mode Protocol
The parallel general purpose I/O (GPIO) boot mode asynchronously transfers code from GPIO0 -GPIO5,
GPIO8-GPIO9 to internal memory. Each value is 8 bits long and follows the same data flow as outlined in
Figure 6-27.
Figure 6-27. Overview of Parallel GPIO Bootloader Operation
Control
subsystem
boot ROM
The control subsystem communicates with the external host device by polling/driving the GPIO27 and
GPIO26 lines. The handshake protocol shown in
word via GPIO [9,8,5:0]. This protocol is very robust and allows for a slower or faster host to communicate
with the master subsystem.
Two consecutive 8-bit words are read to form a single 16-bit word. The most significant byte (MSB) is read
first followed by the least significant byte (LSB). In this case, data is read from GPIO[9,8,5:0].
The 8-bit data stream is shown in
SPRUHE8E – October 2012 – Revised November 2019
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28x control − GPIO26
Host control − GPIO27
8
Data GP I/O port GPIO[9,8,5:0]
Figure 6-28
Table 6-28.
Copyright © 2012–2019, Texas Instruments Incorporated
C-Boot ROM Description
Host
(data and program
source)
must be used to successfully transfer each
ROM Code and Peripheral Booting
653