Enhanced Sci Module Overview; Sci Cpu Interface - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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13.1 Enhanced SCI Module Overview

The SCI interfaces are shown in
GPIO SCITXD
MUX
SCIRXD
Features of the SCI module include:
• Two external pins:
– SCITXD: SCI transmit-output pin
– SCIRXD: SCI receive-input pin
Both pins can be used as GPIO if not used for SCI.
• Baud rate programmable to 64K different rates
• Data-word format
– One start bit
– Data-word length programmable from one to eight bits
– Optional even/odd/no parity bit
– One or two stop bits
• Four error-detection flags: parity, overrun, framing, and break detection
• Two wake-up multiprocessor modes: idle-line and address bit
• Half- or full-duplex operation
• Double-buffered receive and transmit functions
• Transmitter and receiver operations can be accomplished through interrupt- driven or polled algorithms
with status flags.
• Separate enable bits for transmitter and receiver interrupts (except BRKDT)
• NRZ (non-return-to-zero) format
• 13 SCI module control registers located in the control register frame beginning at address 7050h
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
register is accessed, the register data is in the lower byte (7−0), and the upper byte (15−8) is read as
zeros. Writing to the upper byte has no effect.
Enhanced features:
SPRUHE8E – October 2012 – Revised November 2019
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Figure 13-1.
Figure 13-1. SCI CPU Interface
System
Low speed
control
prescaler
block
SCIENCLK LSPCLK
SCI
Copyright © 2012–2019, Texas Instruments Incorporated
Enhanced SCI Module Overview
SYSCLKOUT
CPU
SYSRS
RXINT
TXINT
C28 Serial Communications Interface (SCI)
PIE
block
1017