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Table 17-40. EPI Host-Bus 8 Configuration 4 Register (EPIHB8CFG4) Field Descriptions
Bit
Field
31-22
Reserved
21
WRHIGH
20
RDHIGH
19
ALEHIGH
18-8
Reserved
7-6
WRWS
5-4
RDWS
3-2
Reserved
1-0
MODE
SPRUHE8E – October 2012 – Revised November 2019
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Value
Description
Reserved
CS3 WRITE Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB8CFG2 .
0
The WRITE strobe for CS3 accesses is WR (active Low).
1
The WRITE strobe for CS3 accesses is WR (active High).
C32 READ Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB8CFG2.
0
The READ strobe for CS3 accesses is RD (active Low).
1
The READ strobe for CS3 accesses is RD (active High).
CS3 ALE Strobe Polarity
This field is used if the CSBAUD bit is enabled in EPIHB8CFG2.
0
The address latch strobe for CS3 accesses is ADV (active Low).
1
The address latch strobe for CS3 accesses is ALE (active High).
Reserved
CS3 Write Wait States
This field is used in conjunction with the EPIBAUD register.
This field adds wait states to the data phase of CS3 accesses (the address phase is not affected).
The effect is to delay the rising edge of WR (or the falling edge of WR). Each wait state adds two
EPI clock cycles to the access time. The WRWSM bit in the EPIHB8TIME4 register can decrease
the number of wait states by one EPI clock cycle for greater granularity. This field is used if the
CSBAUD bit is enabled in the EPIHB8CFG2 register. This field is not applicable in BURST mode.
0x0
Active WR is 2 EPI clocks
0x1
Active WR is 4 EPI clocks
0x2
Active WR is 6 EPI clocks
0x3
Active WR is 8 EPI clocks
CS3 Read Wait States
This field is used in conjunction with the EPIBAUD register.
This field adds wait states to the data phase of CS3 accesses (the address phase is not affected).
The effect is to delay the rising edge of RD/OE (or the falling edge of RD). Each wait state adds two
EPI clock cycles to the access time. The RDWSM bit in the EPIHB8TIME4 register can decrease
the number of wait states by one EPI clock cycle for greater granularity. This field is used if the
CSBAUD bit is enabled in the EPIHB8CFG2 register. This field is not applicable in BURST mode.
0x0
Active RD is 2 EPI clocks
0x1
Active RD is 4 EPI clocks
0x2
ActiveRD is 6 EPI clocks
0x3
Active RD is 8 EPI clocks
Reserved
CS3 Host Bus Sub-Mode
This field determines which Host Bus 8 sub-mode to use for CS3 in multiple chip-select mode.
Sub-mode use is determined by the connected external peripheral. See
on how this bit field affects the operation of the EPI signals.
Note: The CSBAUD bit must be set to enable this CS3 MODE field. If CSBAUD is clear, all chip
selects use the MODE configuration defined in the EPIHB8CFG register.
0x0
ADMUX – AD[7:0]
Data and Address are muxed.
0x1
ADNONMUX – D[7:0]
Data and address are separate.
0x2
Continuous Read - D[7:0]
This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OE
strobing.
0x3
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Register Descriptions
Table 17-6
for information
External Peripheral Interface (EPI)
1303
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