Usbrxcsrh[15]); Usb Receive Control And Status Endpoint N High Register (Usbcsrh[N]) In Otg A/Host Mode; Usb Control And Status Endpoint N High Register (Usbcsrh[N]) In Otg A/Host Mode Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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18.5.38 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]-

USBRXCSRH[15])

The USB receive control and status endpoint n high 8-bit register (USBCSRL[n]) provides additional
control and status bits for transfers through the currently selected receive endpoint.
For the specific offset for each register see
Mode(s): OTG A or Host
The USBCSRH[n] registers in OTG A/Host mode are shown in
51.
Figure 18-48. USB Receive Control and Status Endpoint n High Register (USBCSRH[n]) in OTG
7 6
AUTOCL AUTORQ
W1C-0 R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 18-51. USB Control and Status Endpoint n High Register (USBCSRH[n])
Bit Field Value
7 AUTOCL
0
1
6 AUTORQ
0
1
5 DMAEN
0
1
4 PIDERR
0
1
3 DMAMOD
0
1
2 DTWE
0
1
1 DT
0 Reserved 0
SPRUHE8E – October 2012 – Revised November 2019
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Table
OTG B or Device
A/Host Mode
5 4
DMAEN PIDERR
R/W-0 R-0
in OTG A/Host Mode Field Descriptions
Description
Auto Clear
No effect
Enables the RXRDY bit to be automatically cleared when a packet of USBRXMAXP[n] bytes has been
unloaded from the receive FIFO. When packets of less than the maximum packet size are unloaded,
RXRDY must be cleared manually. Care must be taken when using μDMA to unload the receive FIFO
as data is read from the receive FIFO in 4-byte chunks regardless of the value of the MAXLOAD field in
the USBRXMAXP[n] register, see
Auto Request
Note: This bit is automatically cleared when a short packet is received.
No effect
Enables the REQPKT bit to be automatically set when the RXRDY bit is cleared.
DMA Request Enable
Note: Three TX and three RX endpoints can be connected to the μDMA module. If this bit is set for a
particular endpoint, the DMAARX, DMABRX, or DMACRX field in the USB DMA Select (USBDMASEL)
register must be programmed correspondingly.
Disables the μDMA request for the receive endpoint.
Enables the μDMA request for the receive endpoint.
PID Error. This bit is ignored in bulk or interrupt transactions.
No error
Indicates a PID error in the received packet of an isochronous transaction.
DMAMOD
Note: This bit must not be cleared either before or in the same cycle as the above DMAEN bit is
cleared.
An interrupt is generated after every μDMA packet transfer.
An interrupt is generated only after the entire μDMA transfer is complete.
Data Toggle Write Enable. This bit is automatically cleared once the new value is written.
The DT bit cannot be written.
Enables the current state of the receive endpoint data to be written (see DT bit).
Data Toggle. When read, this bit indicates the current state of the receive data toggle.
If DTWE is High, this bit may be written with the required setting of the data toggle. If DTWE is Low, any
value written to this bit is ignored. Care should be taken when writing to this bit as it should only be
changed to RESET the receive endpoint.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
18-4.
Figure 18-48
3 2
DMAMOD DTWE
R/W-0 R-0
Section 18.2.4.
M3 Universal Serial Bus (USB) Controller
Register Descriptions
and described in Table 18-
1 0
DT Reserved
R-0 R-0
1385