Device Bring-Up Time Line - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Time Line Master Subsystem
POR indicates that device is not yet
T0
fully powered and is in reset
Master subsystem out of reset. Device
T1 Specific initialization as mentioned in
the Boot ROM guide.
T2 Bring control subsystem out of reset
T3 Bring ACIB out of reset
Master bootROM boots the device
T4 based on the boot mode GPIO
configuration.
T5 Running application on master
Below are the details on each reset source.
1.3.1.1 Power-on Reset (POR):
The Analog and Digital Subsystems' each have a Power-On-Reset (POR) circuit that creates a clean reset
throughout the device enabling glitchless GPIOs during the power-on procedure. The POR function keeps
both ARS and XRS driven low during device power up. Whenever the device is reset by a POR condition,
bit 1 of the MRESC register is set indicating that the POR has caused a reset, and because a POR reset
pulls the XRS pin low, bit 0 is also set.
NOTE: The power-on reset also resets the JTAG controller.
While in most applications, the POR generated reset has a long enough duration to also reset other
system ICs, some applications may require a longer lasting pulse. In these cases, the ARS and XRS reset
pins (which are open-drain) can also be driven low to match the time the device is held in a reset state
with the rest of the system.
When the device is reset by a POR condition, the master subsystem begins executing the master Boot
ROM and brings the control subsystem and analog subsystem out of reset. Once out of reset, the control
subsystem starts executing its code in C-Boot ROM. Please refer to the Boot ROM chapter for how both
the master subsystem boot ROM and control subsystem boot ROM handle this reset cause.
1.3.1.2 External Reset Input
There are two external reset input pins on the device: XRS and ARS.
The XRS and ARS pins both respond to an external reset signal (active low), and can also drive the reset
signal out of the chip to external circuitry whenever any of the internal digital or analog subsystem resets
become active, as shown in the
master subsystem watchdog modules (WDT0, WDT1 and MNMIWD). Whenever the master subsystem is
reset by an XRS condition, it will hold both control and analog subsystems in reset and bit 0 of the
MRESC register will be set to indicate an XRS caused the reset. When the device is out of reset, the
master subsystem Boot ROM will start executing and it will bring both control and analog systems out of
reset. Once out of reset, the control subsystem will start executing its own Boot ROM. Please refer to the
Boot ROM chapter for how both the master and control boot ROMs handle an XRS reset.
It is recommended to connect both XRS and ARS pins together externally using a single trace.
The internal reset which can pull ARS low is caused by the power-on reset (POR).
SPRUHE8E – October 2012 – Revised November 2019
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Table 1-4. Device Bring-Up Time Line
Control Subsystem
POR indicates that device is not yet
fully powered and is in reset
Control subsystem held in reset
Control subsystem starts executing C-
Boot ROM
After system initialization, the C28x
CPU goes to IDLE mode; wakes up on
IPC interrupts
Master Application decides how to run
application on control subsystem.
Table 1-3. The internal resets which pull XRS low are caused by the
Copyright © 2012–2019, Texas Instruments Incorporated
Reset Control
Analog Subsystem/ACIB
POR indicates that device is not yet
fully powered and is in reset
Analog subsystem/ACIB held in reset
Analog subsystem/ACIB held in reset
Analog subsystem/ACIB out of reset
and analog peripherals are accessible
for both master and control
subsystems.
ACIB and analog peripherals ready to
be configured, controlled and
monitored by control subsystem
application and master subsystem
application.
System Control and Interrupts
85