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Functional Description
Figure 20-9. Freescale SPI Frame Format with SPO =1 and SPH =1
SSIClk
SSIFss
SSIRx
SSITx
In this configuration, during idle periods:
•
SSIClk is forced hgh
•
SSIFss is forced high
•
The transmit data line SSITx is arbitrarily forced low
•
When the SSI is configured as a master, it enables the SSIClk pad
•
When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the
SSIFss master signal being driven low. The master SSITx output pad is enabled. After an additional one-
half SSIClk period, both master and slave data are enabled onto their respective transmission lines. At the
same time, SSIClk is enabled with a falling edge transition. Data is then captured on the rising edges and
propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is returned
to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active low state until the final bit
of the last word has been captured and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSIFss pin is held low between successive data words and
termination is the same as that of the single word transfer.
20.3.5 DMA Operation
The SSI peripheral provides an interface to the µDMA controller with separate channels for transmit and
receive. The µDMA operation of the SSI is enabled through the SSI DMA Control (SSIDMACTL) register.
When µDMA operation is enabled, the SSI asserts a µDMA request on the receive or transmit channel
when the associated FIFO can transfer data. For the receive channel, a single transfer request is asserted
whenever any data is in the receive FIFO. A burst transfer request is asserted whenever the amount of
data in the receive FIFO is four or more items.
For the transmit channel, a single transfer request is asserted whenever at least one empty location is in
the transmit FIFO. The burst request is asserted whenever the transmit FIFO has four or more empty
slots. The single and burst µDMA transfer requests are handled automatically by the µDMA controller
depending how the µDMA channel is configured. To enable µDMA operation for the receive channel, the
RXDMAE bit of the DMA Control (SSIDMACTL) register should be set. To enable µDMA operation for the
transmit channel, the TXDMAE bit of SSIDMACTL should be set. If µDMA is enabled, then the µDMA
controller triggers an interrupt when a transfer is complete. The interrupt occurs on the SSI interrupt
vector. Therefore, if interrupts are used for SSI operation and µDMA is enabled, the SSI interrupt handler
must be designed to handle the µDMA completion interrupt.
If the μDMA is enabled and has completed a data transfer from the Tx FIFO, the DMATXRIS bit is set in
the SSIRIS register and cannot be cleared by setting the DMATXIC bit in the SSI Interrupt Clear (SSIICR)
register. In the DMA Completion Interrupt Service Routine, software must disable the μDMA transmit
enable to the SSI by clearing the TXDMAE bit in the SSI DMA Control (SSIDMACTL) register and then
setting the DMATXIC bit in the SSIICR register. This clears the DMA completion interrupt. When the
μDMA is needed to transmit more data, the TXDMAE bit must be set (enabled) again. If a data transfer by
the μDMA from the Rx FIFO completes, the DMARXRIS bit is set. The EOT bit in the SSIRIS register is
also provided to indicate when the Tx FIFO is empty and the last bit has been transmitted out of the
serializer.
1454
M3 Synchronous Serial Interface (SSI)
MSB
Q
MSB
Copyright © 2012–2019, Texas Instruments Incorporated
4 to16 bits
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
LSB
Q
LSB
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