Priority Control Register (Scipri); Sci Priority Control Register (Scipri) - Address 705Fh; Sci Priority Control Register (Scipri) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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13.3.10 Priority Control Register (SCIPRI)

Figure 13-25. SCI Priority Control Register (SCIPRI) — Address 705Fh
7
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13-18. SCI Priority Control Register (SCIPRI) Field Descriptions
Bit Field
7-5 Reserved
4-3 SOFT and FREE
2-0 Reserved
SPRUHE8E – October 2012 – Revised November 2019
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5 4
SCI SOFT
R/W-0
Value Description
Reads return zero; writes have no effect.
These bits determine what occurs when an emulation suspend event occurs (for example, when the
debugger hits a breakpoint). The peripheral can continue whatever it is doing (free-run mode), or if
in stop mode, it can either stop immediately or stop when the current operation (the current
receive/transmit sequence) is complete.
00 Immediate stop on suspend
10 Complete current receive/transmit sequence before stopping
x1 Free run. Continues SCI operation regardless of suspend
Reads return zero; writes have no effect.
Copyright © 2012–2019, Texas Instruments Incorporated
3 2
SCI FREE
R/W-0
C28 Serial Communications Interface (SCI)
SCI Registers
0
Reserved
R-0
1043