Mcbsp Transmission; Mcbsp Transmission Physical Data Path; Mcbsp Transmission Signal Activity - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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• Overrun in the Receiver (see
• Unexpected Receive Frame-Synchronization Pulse (see

15.3.6 McBSP Transmission

This section explains the fundamental process of transmission in the McBSP. For details about how to
program the McBSP transmitter, see
Figure 15-15 and Figure 15-16
physical path for the data.
transmission scenario. A description of the process follows the figures.
DX
A XSR[1,2]: Transmit shift registers 1 and 2
B DXR[1,2]: Data transmit registers 1 and 2
CLKX
FSX
A1 A0
DX
XRDY
DXR1 to XSR1 copy(B)
A CLKX: Internal transmit clock
B FSX: Internal transmit frame-synchronization signal
C DX: Data on DX pin
D XRDY: Status of transmitter ready bit (high is 1)
1. The CPU or the DMA controller writes data to the data transmit register(s). When DXR1 is loaded, the
transmitter ready bit (XRDY) is cleared in SPCR2 to indicate that the transmitter is not ready for new
data.
If the word length is 16 bits or smaller, only DXR1 is used. If the word length is larger than 16 bits,
DXR2 and DXR1 are used and DXR2 contains the most significant bits. For details on choosing a word
length, see Section
NOTE: If both DXRs are needed (word length larger than 16 bits), the CPU or the DMA controller
must load DXR2 first and then load DXR1. As soon as DXR1 is loaded, the contents of both
DXRs are copied to the transmit shift registers (XSRs), as described in the next step. If
DXR2 is not loaded first, the previous content of DXR2 is passed to the XSR2.
2. When new data arrives in DXR1, the McBSP copies the content of the data transmit register(s) to the
transmit shift register(s). In addition, the transmit ready bit (XRDY) is set. This indicates that the
transmitter is ready to accept new data from the CPU or the DMA controller.
If the word length is 16 bits or smaller, only XSR1 is used. If the word length is larger than 16 bits,
XSR2 and XSR1 are used and XSR2 contains the most significant bits.
If companding is used during the transfer (XCOMPAND = 10b or 11b in XCR2), the McBSP
compresses the 16-bit data in DXR1 to 8-bit data in the μ-law or A-law format in XSR1. If companding
is disabled, the McBSP passes data from the DXR(s) to the XSR(s) without modification.
3. The McBSP waits for a transmit frame-synchronization pulse on internal FSX.
4. When the pulse arrives, the McBSP inserts the appropriate data delay that is selected with the
XDATDLY bits of XCR2.
SPRUHE8E – October 2012 – Revised November 2019
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Section 15.5.2)
Section
show how transmission occurs in the McBSP.
Figure 15-16 is a timing diagram showing signal activity for one possible
Figure 15-15. McBSP Transmission Physical Data Path
XSR[1,2]
Compress
or
do not modify
Figure 15-16. McBSP Transmission Signal Activity
B7 B6 B5 B4
Write to DXR1(C)
15.9.8, Set the Transmit Word Length(s).
Copyright © 2012–2019, Texas Instruments Incorporated
Section 15.5.3)
15.9, Transmitter Configuration.
DXR[1,2]
B3 B2 B1 B0
DXR1 to XSR1 copy(C)
C28 Multichannel Buffered Serial Port (McBSP)
Frame Phases
Figure 15-15 shows the
From CPU or
DMA controller
C7 C6 C5
Write to DXR1
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