Control Subsystem Nmi Sources And Cnmiwd - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Exceptions and Interrupts Control

CNMIFLG[NMIINT]

NMI INT TO C28 CPU

CNMIWDPRD[15:0]

CNMIWDCNT[15:0]

Flag Force (CNMIFLGFRC) register to simulate an NMI error condition to aid in debug and development.

When an NMI error event occurs:

Respective bit in the CNMIFLG register is set

NMIINT bit in the CNMIFLG register is set

CNMIWD timer is triggered and starts counting

The user has to handle the error condition that triggered the NMI by checking the individual flag bits in the

CNMIFLG register, clearing the set bits in the CNMIFLG register, and clearing the NMIINT bit in the

CNMIFLG register. Clearing the NMIINT bit in the CNMIFLG register will stop and reset the CNMIWD

counter back to zero. If the NMIINT bit is not cleared by the time the CNMIWD counter reaches the value

programmed in the CNMIWDPRD register, the control subsystem is reset and an NMI is triggered to the

master subsystem NMI block.

Control Subsystem NMI Sources

This section explains the error events that can generate an NMI to the control subsystem CPU.

System Control and Interrupts

Figure 1-9. Control Subsystem NMI Sources and CNMIWD

Refer "Resets" Section

1-9, any of the listed errors can trigger an NMI to the C28x CPU There is also an NMI

CNMIFLG[RAM UNC ERR]

CNMIFLGCLR[RAM UNC ERR]

CNMIFLG[CLOCKFAIL]

CNMIFLG[FLUNCERR]

CNMIFLG[ACIBERR]

SPRUHE8E – October 2012 – Revised November 2019

CNMIFLGFRC[RAMUNCERR]

FLASH UNC ERROR

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