Dual- And Quad- Chip Select Address Mappings - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Host Bus Mode
In quad chip select mode (CSCFGEXT is 0x1 and CSCFG is 0x1 or 0x2 in the EPIHBnCFG2 register),
both the peripheral and the memory space must be enabled.
In the EPIADDRMAP register, the EPADR field is 0x3, the ERADR field is 0x3, and the ECADR field is
0x0. With this configuration, CS0 asserts for the address range beginning at 0x6000.0000, CS1 asserts for
0x8000.0000, CS2 for 0xA000.0000, and CS3 for 0xC000.0000.
Table 17-3 gives a detailed explanation of chip select address range mappings based on combinations of
enabled peripheral and memory space.
Chip Select
ERADR
Mode
Dual-chip
select
Dual-chip
0x1 or 0x2
select
Dual-chip
0x1 or 0x2
select
Dual-chip
select
Dual-chip
0x1 or 0x2
select
Quad-chip
select
Tri-chip select
(1)
When CS0 and CS1 share address space, CS0 asserts when the MSB of the address is '0' and CS1, when the MSB of the
address is '1'.
The MODE field of the EPIHBnCFGn registers configure the interface for the chip selects, which support
ADMUX or ADNOMUX. See
select. If the CSBAUD bit is clear, all chip selects are configured by the MODE bit field of the EPIHBnCFG
register.
If the CSBAUD bit in the EPIHBnCFG2 register is set in dual-chip select mode, the two chip selects can
use different clock frequencies, wait states and strobe polarity. If the CSBAUD bit is clear, both chip
selects use the clock frequency, wait states, and strobe polarity defined for CS0. Additionally, if the
CSBAUD bit is set, the two chip selects can use different interface modes. If any interface modes are
programmed to ADMUX, then dual chip select mode must include the ALE capability. In quad chip select
mode, if the CSBAUD bit in the EPIHBnCFG2 register is set, the four chip selects can use different clock
frequencies, wait states and strobe polarity. If the CSBAUD bit is clear, all chip selects use the clock
frequency, wait states, and strobe polarity defined for CS0. If the CSBAUD bit is set, the four chip selects
can use different interface modes
1238
External Peripheral Interface (EPI)
Table 17-3. Dual- and Quad- Chip Select Address Mappings
EPADR
0x0 0x1 or 0x2
0x0
0x1 or 0x2
0x0 0x1 or 0x2
0x0
0x3 0x3
0x3 0x3
Table 17-4 for details on which configuration register controls each chip
Copyright © 2012–2019, Texas Instruments Incorporated
(1)
ECADR CS0
EPADR
defined
address range address range
0x0
(0xA000.0000 (0xA000.0000
or
0xC000.0000) 0xC000.0000)
ERADR
defined
address range address range
0x0
(0x6000.0000 (0x6000.0000
or
0x8000.000) 0x8000.000)
EPADR
defined
address range address range
0x0
(0xA000.0000 (0x6000.0000
or
0xC000.0000) 0x8000.0000)
ECADR
defined address range
0x1
address range (0xA000.0000
(0x1000.0000)
0xC000.0000)
ECADR
defined address range
0x1
address range (0x6000.0000
(0x1000.0000)
0x8000.0000)
0x0 0x6000.0000 0x8000.0000
0x0 0x6000.0000
SPRUHE8E – October 2012 – Revised November 2019
CS1 CS2
EPADR
defined
N/A
or
ERADR
defined
N/A
or
ERADR
defined
N/A
or
EPADR
defined
N/A
or
ERADR
defined
N/A
or
0xA000.0000 0xC000.0000
N/A 0xA000.0000 0xC000.0000
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CS3
N/A
N/A
N/A
N/A
N/A