Architecture; Sci-A Registers; Sci-B Registers - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Name
SCICCR
SCICTL1
SCIHBAUD
SCILBAUD
SCICTL2
SCIRXST
SCIRXEMU
SCIRXBUF
SCITXBUF
SCIFFTX
SCIFFRX
SCIFFCT
SCIPRI
Name
SCICCR
SCICTL1
SCIHBAUD
SCILBAUD
SCICTL2
SCIRXST
SCIRXEMU
SCIRXBUF
SCITXBUF
SCIFFTX
SCIFFRX
SCIFFCT
SCIPRI
(1)
The registers are mapped to peripheral frame 2. This frame allows only 16-bit accesses. Using 32-bit accesses will produce
undefined results.
(2)
SCIB is an optional peripheral. In some devices this may not be present. See the device-specific data sheet for peripheral
availability.

13.1.1 Architecture

The major elements used in full-duplex operation are shown in
A transmitter (TX) and its major registers (upper half of
– SCITXBUF — transmitter data buffer register. Contains data (loaded by the CPU) to be transmitted
– TXSHF register — transmitter shift register. Accepts data from register SCITXBUF and shifts data
onto the SCITXD pin, one bit at a time
A receiver (RX) and its major registers (lower half of
– RXSHF register — receiver shift register. Shifts data in from SCIRXD pin, one bit at a time
– SCIRXBUF — receiver data buffer register. Contains data to be read by the CPU. Data from a
remote processor is loaded into register RXSHF and then into registers SCIRXBUF and
SCIRXEMU
SPRUHE8E – October 2012 – Revised November 2019
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Table 13-1. SCI-A Registers
Address Range
Size (x16)
0x0000-7050
0x0000-7051
0x0000-7052
0x0000-7053
0x0000-7054
0x0000-7055
0x0000-7056
0x0000-7057
0x0000-7059
0x0000-705A
0x0000-705B
0x0000-705C
0x0000-705F
Table 13-2. SCI-B Registers
Address Range
0x0000-7750
0x0000-7751
0x0000-7752
0x0000-7753
0x0000-7754
0x0000-7755
0x0000-7756
0x0000-7757
0x0000-7759
0x0000-775A
0x0000-775B
0x0000-775C
0x0000-775F
Copyright © 2012–2019, Texas Instruments Incorporated
Description
1
SCI-A Communications Control Register
1
SCI-A Control Register 1
1
SCI-A Baud Register, High Bits
1
SCI-A Baud Register, Low Bits
1
SCI-A Control Register 2
1
SCI-A Receive Status Register
1
SCI-A Receive Emulation Data Buffer Register
1
SCI-A Receive Data Buffer Register
1
SCI-A Transmit Data Buffer Register
1
SCI-A FIFO Transmit Register
1
SCI-A FIFO Receive Register
1
SCI-A FIFO Control Register
1
SCI-A Priority Control Register
(1) (2)
Size (x16)
Description
1
SCI-B Communications Control Register
1
SCI-B Control Register 1
1
SCI-B Baud Register, High Bits
1
SCI-B Baud Register, Low Bits
1
SCI-B Control Register 2
1
SCI-B Receive Status Register
1
SCI-B Receive Emulation Data Buffer Register
1
SCI-B Receive Data Buffer Register
1
SCI-B Transmit Data Buffer Register
1
SCI-B FIFO Transmit Register
1
SCI-B FIFO Receive Register
1
SCI-B FIFO Control Register
1
SCI-B Priority Control Register
Figure 13-2
Figure
13-2)
Figure
13-2)
C28 Serial Communications Interface (SCI)
Enhanced SCI Module Overview
and include:
1019

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