Dma Configuration (Dmacfg), Offset 0X004; Dma Channel Control Base Pointer (Dmactlbase), Offset 0X008; Dma Configuration (Dmacfg) Register; Dma Channel Control Base Pointer (Dmactlbase) Register - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 16-17. DMA Status (DMASTAT) Register Field Descriptions (continued)

16.7.2 DMA Configuration (DMACFG), offset 0x004

The DMACFG register controls the configuration of the µDMA controller.

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16-18. DMA Configuration (DMACFG) Register Field Descriptions

The DMACTLBASE register must be configured so that the base pointer points to a location in system

The amount of system memory that must be assigned to the µDMA controller depends on the number of

µDMA channels used and whether the alternate channel control data structure is used. See

for details about the Channel Control Table. The base address must be aligned on a 1024-byte boundary.

This register cannot be read when the µDMA controller is in the reset state.

Figure 16-12. DMA Channel Control Base Pointer (DMACTLBASE) Register

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

SPRUHE8E – October 2012 – Revised November 2019

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Control State Machine Status

This field shows the current status of the control state machine. Status can be one of the following.

Reading channel controller data.

Reading source end pointer.

Reading destination end pointer.

Reading source data.

Writing destination data.

Waiting for μDMA request to clear.

Writing channel controller data.

Master Enable Status

The μDMA controller is disabled.

The μDMA controller is enabled.

Figure 16-11. DMA Configuration (DMACFG) Register

Controller Master Enable

Disables the μDMA controller.

Enables μDMA controller.

µDMA Register Descriptions

M3 Micro Direct Memory Access ( µDMA)

Section 16.3.5

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