Error Counter Register (Can Errc) [Offset = 0X08]; Bit Timing Register (Can Btr) [Offset = 0X0C]; Error Counter Register Field Descriptions; Bit Timing Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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NOTE: For debug support, the auto clear functionality of Error and Status Register (clear of status
flags by read) is disabled when in Debug mode.
23.15.3 Error Counter Register (CAN ERRC)
The Error Counter register (CAN ERRC) is shown and described in the figure and table below.
31
15 14
RP
R-0
LEGEND: R = Read; -n = value after reset
Bit Field
31-16 Reserved
15 RP
14-8 REC[6:0]
7-0 TEC[7:0]
23.15.4 Bit Timing Register (CAN BTR)
The Bit Timing register (CAN BTR) is shown and described in the figure and table below.
31
15 14 12
Rsvd TSeg2
R-0 R/WP-0x2
LEGEND: R = Read; WP = Write Protected by CCE bit; -n = value after reset
Bit Field
31-20 Reserved
19-16 BRPE
15 Reserved
14-12 TSeg2 0x0-0x7 Time segment after the sample point Valid programmed values are 0 to 7. The actual TSeg2 value
11-8 TSeg1
7-6 SJW 0x0-0x3 Synchronization Jump Width Valid programmed values are 0 to 3. The actual SJW value
SPRUHE8E – October 2012 – Revised November 2019
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Figure 23-21. Error Counter Register (CAN ERRC) [offset = 0x08]
REC[6:0]
R-0
Table 23-7. Error Counter Register Field Descriptions
Value Description
Reserved
Receive Error Passive
0 The Receive Error Counter is below the error passive level.
1 The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
Receive Error Counter. Actual state of the Receive Error Counter (values from 0 to 255).
Transmit Error Counter. Actual state of the Transmit Error Counter (values from 0 to 255).
Figure 23-22. Bit Timing Register (CAN BTR) [offset = 0x0C]
Reserved
R-0
11
TSeg1
R/WP-0x3
Table 23-8. Bit Timing Register Field Descriptions
Value Description
Reserved
0x00- Baud Rate Prescaler Extension. Valid programmed values are 0 to 15. By programming BRPE the
0x0F Baud Rate Prescaler can be extended to values up to 1024.
Reserved
which is interpreted for the Bit Timing will be the programmed TSeg2 value + 1.
0x01- Time segment before the sample point Valid programmed values are 1 to 15. The actual TSeg1
0x0F value interpreted for the Bit Timing will be the programmed TSeg1 value + 1.
interpreted for the Synchronization will be the programmed SJW value + 1.
Copyright © 2012–2019, Texas Instruments Incorporated
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R-0
8 7
8 7 6 5
SJW
R/WP-0
CAN Control Registers
TEC[7:0]
R-0
20 19
BRPE
R/WP-0
BRP
R/WP-0x1
M3 Controller Area Network (CAN)
16
0
16
0
1585