Gpio Commit (Gpiocr) Register; Gpio Analog Mode Select (Gpioamsel) Register; Gpio Commit (Gpiocr) Register Field Descriptions; Gpio Analog Mode Select (Gpioamsel) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

General-Purpose Input/Output (GPIO)
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-8 Reserved
7-0 CR
4.1.6.16 GPIO Analog Mode Select (GPIOAMSEL) Register, offset 0x528
The GPIOAMSEL register selects the analog function of a pin. The appropriate bits need to be set to
enable the USB0VBUS and USB0ID signals for USB0 to function correctly.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-20. GPIO Analog Mode Select (GPIOAMSEL) Register Field Descriptions
Bit Field
31-8 Reserved
7-4 GPIOAMSEL
3-0 Reserved
366
General-Purpose Input/Output (GPIO)
Figure 4-18. GPIO Commit (GPIOCR) Register
R-0
Table 4-19. GPIO Commit (GPIOCR) Register Field Descriptions
Value Description
Reserved
GPIO Commit
0 The corresponding GPIOAFSEL, GPIOPUR, GPIOCSEL, or GPIODEN bits cannot be written.
1 The corresponding GPIOAFSEL, GPIOPUR, GPIOCSEL, or GPIODEN bits can be written.
Note: The default register type for the GPIOCR register is RO for all GPIO pins with the exception
of the NMI pin, PB7. This pin is currently the only GPIO that is protected by the GPIOCR register.
Because of this, the register type for GPIO Port B7 is R/W.
The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the
exception of the NMI pin, PB7. To ensure that the NMI pin is not accidentally programmed as the
non-maskable interrupt pin, it defaults to non-committable. Because of this, the default reset value
of GPIOCR for GPIO Port B is 0x0000.007F.
Figure 4-19. GPIO Analog Mode Select (GPIOAMSEL) Register
R-0
Value Description
Reserved
GPIO Analog Mode Select
0 The analog function of the pin is disabled and the pin is capable of digital functions as specified by
the other GPIO configuration registers.
1 The analog function of the pin is enabled.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
8 7
Reserved
R-0
8 7
GPIOAMSEL
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
CR
-
4 3
Reserved
R-0
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16
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16
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