Master Access Violation Flag Clear Register (Mmavclr); Non-Master Cpu Write Access Violation Address Register (Mnmwravaddr); Master Access Violation Flag Clear Register (Mmavclr) Field Descriptions; Non-Master Cpu Write Access Violation Address Register (Mnmwravaddr) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

RAM Control Module Registers

5.2.2.19 Master Access Violation Flag Clear Register (MMAVCLR)

Figure 5-37. Master Access Violation Flag Clear Register (MMAVCLR)
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-46. Master Access Violation Flag Clear Register (MMAVCLR) Field Descriptions
Bit Field
31-3 Reserved
2 CPUWRITE
1 DMAWRITE
0 CPUFETCH

5.2.2.20 Non-Master CPU Write Access Violation Address Register (MNMWRAVADDR)

Figure 5-38. Non-Master CPU Write Access Violation Address Register (MNMWRAVADDR)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-47. Non-Master CPU Write Access Violation Address Register (MNMWRAVADDR) Field
Bit Field
31-0 NMCPUWRAVADDR
504
Internal Memory
Reserved
R-0
Value Description
Reserved
Master CPU Write Access Violation Clear
0 No effect.
1 Clears the corresponding master CPU write access violation flag.
Master DMA Write Access Violation Clear
0 No effect.
1 Clears the corresponding master DMA write access violation flag.
Master CPU Fetch Access Violation Clear
0 No effect.
1 Clears the corresponding master CPU fetch access violation flag.
NMCPUWRAVADDR
Value Description
Non-Master CPU Write Access Violation Address
This holds the address at which M3 CPU attempted a write access and the non-master
CPU write access violation occurred.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
CPUWRITE
R=0/W=1-0
R-0
Descriptions
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
16
1 0
DMAWRITE CPUFETCH
R=0/W=1-0 R=0/W=1-0
0
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