Uart Receive Status Register (Uartrsr/Uartecr); Uart Receive Status Register (Uartrsr/Uartecr) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Figure 21-8. UART Receive Status Register (UARTRSR/UARTECR)

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21-3. UART Receive Status Register (UARTRSR/UARTECR) Field Descriptions

M3 Universal Asynchronous Receivers/Transmitters (UARTs)

UART Overrun Error

This bit is cleared by a write to UARTECR. The FIFO contents remain valid because no further data

is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must

read the data in order to empty the FIFO.

No data has been lost due to a FIFO overrun.

New data was received when the FIFO was full, resulting in data loss.

UART Break Error

This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the

character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the

FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state)

and the next valid start bit is received.

No break condition has occurred.

A break condition has been detected, indicating that the receive data input was held Low for longer

than a full-word transmission time (defined as start, data, parity, and stop bits).

UART Parity Error

This bit is cleared to 0 by a write to UARTECR.

No parity error has occurred.

The parity of the received data character does not match the parity defined by bits 2 and 7 of the

UARTLCRH register.

UART Framing Error

This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the

character at the top of the FIFO.

No framing error has occurred.

The received character does not have a valid stop bit (a valid stop bit is 1).

SPRUHE8E – October 2012 – Revised November 2019

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