Priority Status Register (Prioritystat); Priority Status Register (Prioritystat) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions

11.8.5 Priority Status Register (PRIORITYSTAT)

The priority status register (PRIORITYSTAT) is shown in
15
7 6
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11-7. Priority Status Register (PRIORITYSTAT) Field Descriptions
Bit Field
15-7 Reserved
6-4 ACTIVESTS_SH
ADOW
3 Reserved
2-0 ACTIVESTS
968
C28 Direct Memory Access (DMA) Module
Figure 11-12. Priority Status Register (PRIORITYSTAT)
4
ACTIVESTS_SHADOW
R-0
Value Description
Reserved
Active Channel Status Shadow Bits: These bits are only useful when CH1 is enabled as a higher
priority channel. When CH1 is serviced, the ACTIVESTS bits are copied to the shadow bits and
indicate which channel was interrupted by CH1. When CH1 service is completed, the shadow bits
are copied back to the ACTIVESTS bits. If this bit field is zero or the same as the ACTIVESTS bit
field, then no channel is pending due to a CH1 interrupt. When CH1 is not a higher priority channel,
these bits should be ignored:
0,0,0 No channel pending
0,0,1 CH 1
0,1,0 CH 2
0,1,1 CH 3
1,0,0 CH 4
1,0,1 CH 5
1,1,0 CH 6
Reserved
Active Channel Status Bits: These bits indicate which channel is currently active or performing a
transfer:
0,0,0 no channel active
0,0,1 CH 1
0,1,0 CH 2
0,1,1 CH 3
1,0,0 CH 4
1,0,1 CH 5
1,1,0 CH 6
Copyright © 2012–2019, Texas Instruments Incorporated
Figure 11-12 and described in
Reserved
R-0
3 2
Reserved
R-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Table 11-7.
8
0
ACTIVESTS
R-0
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