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1.13.5.2 M3NMI Flag (MNMIFLG) Register
31
15
7
6
C28PIENMIERR
EXTGPIO
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-10
Reserved
9
ACIBERR
8
C28NMIWDRST
7
C28PIENMIERR
6
EXTGPIO
5
C28BISTERR
4
M3BISTERR
1
CLOCKFAIL
SPRUHE8E – October 2012 – Revised November 2019
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Figure 1-62. M3NMI Flag (MNMIFLG) Register
Reserved
R-0
5
4
C28BISTERR
M3BISTERR
R/W-1
R/W-1
Table 1-73. M3NMI Flag (MNMIFLG) Register Field Descriptions
Value
Description
Reserved
CIB Error NMI Flag
This bit indicates if there is a stuck condition on the CIB INTS or CIB READY signals causing an
NMI condition. This bit can only be cleared by the user writing to the corresponding clear bit in the
NMIFLGCLR register or by an XRS reset.
0
No CIB INTS or READY stuck error condition pending
1
CIB INTS or READY stuck error condition generated
C28 NMI WD Reset Flag
This bit indicates that a reset was issued by the C28 NMIWD since the C28 did not service its NMI
interrupt. Once enabled, the flag cannot be cleared by the user. This bit can only be cleared by the
user writing to the corresponding clear bit in the NMIFLGCLR register or by an XRS reset.
0
No C28 NMI WD RST condition pending
1
C28 NMI WD RST condition generated
C28 PIE NMIERR NMI Flag
This bit indicates that an error condition was generated during NMI vector fetch from C28 PIE.
Once enabled, the flag cannot be cleared by the user. This bit can only be cleared by the user
writing to the corresponding clear bit in the NMIFLGCLR register or by an XRS reset.
0
No C28 PIE NMIERR condition pending
1
C28 PIE NMIERR condition generated
External GPIO NMI Flag
This bit indicates if the external GPIO pin generated an NMI interrupt. The bit can only be cleared
by the user writing to the respective bit in the NMIFLGCLR register or by an XRS reset.
0
No external GPIO NMI pending
1
External GPIO NMI condition pending
HW BIST Error NMI Flag: This bit indicates if the time out error or a signature mismatch error
condition during hardware BIST of M3 occurred. This bit can only be cleared by the user writing to
the corresponding clear bit in the NMIFLGCLR register or by an XRSn reset.
0
No C28 HWBIST error condition pending
1
C28 BIST error condition generated
HW BIST Error NMI Flag: This bit indicates if the time out error or a signature mismatch error
condition during hardware BIST of M3 occurred. This bit can only be cleared by the user writing to
the corresponding clear bit in the NMIFLGCLR register or by an XRSn reset.
0
No M3 HWBIST error condition pending
1
M3 BIST error condition generated
Clock Fail NMI Flag
This bit indicates if the CLOCKFAIL condition is latched. These bits can only be cleared by the user
writing to the respective bit in the NMIFLGCLR register or by an XRS reset.
0
No CLOCKFAIL condition pending
1
CLOCKFAIL condition generated
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0:0
10
3
2
Reserved
R-0:0
System Control Registers
9
8
ACIBERR
C28NMIWDRST
R-0
R-0
1
0
CLOCKFAIL
NMIINT
R-0
R-0
System Control and Interrupts
16
203
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