Ecap Interrupt Forcing Register (Ecfrc); Ecap Interrupt Clear Register (Ecclr) Field Descriptions; Ecap Interrupt Forcing Register (Ecfrc) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 8-11. ECAP Interrupt Clear Register (ECCLR) Field Descriptions
Bits Field
15:8 Reserved
7 CTR=CMP
6 CTR=PRD
5 CTROVF
4 CEVT4
3 CEVT3
2 CEVT2
1 CEVT1
0 INT
15 14
7 6
CTR=CMP CTR=PRD
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8-12. ECAP Interrupt Forcing Register (ECFRC) Field Descriptions
Bits Field
15:8 Reserved
7 CTR=CMP
6 CTR=PRD
SPRUHE8E – October 2012 – Revised November 2019
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Description
Any writes to these bit(s) must always have a value of 0.
Counter Equal Compare Status Flag
0 Writing a 0 has no effect. Always reads back a 0
1 Writing a 1 clears the CTR=CMP flag condition
Counter Equal Period Status Flag
0 Writing a 0 has no effect. Always reads back a 0
1 Writing a 1 clears the CTR=PRD flag condition
Counter Overflow Status Flag
0 Writing a 0 has no effect. Always reads back a 0
1 Writing a 1 clears the CTROVF flag condition
Capture Event 4 Status Flag
0 Writing a 0 has no effect. Always reads back a 0.
1 Writing a 1 clears the CEVT4 flag condition.
Capture Event 3 Status Flag
0 Writing a 0 has no effect. Always reads back a 0.
1 Writing a 1 clears the CEVT3 flag condition.
Capture Event 2 Status Flag
1 Writing a 0 has no effect. Always reads back a 0.
0 Writing a 1 clears the CEVT2 flag condition.
Capture Event 1 Status Flag
0 Writing a 0 has no effect. Always reads back a 0.
1 Writing a 1 clears the CEVT1 flag condition.
Global Interrupt Clear Flag
0 Writing a 0 has no effect. Always reads back a 0.
1 Writing a 1 clears the INT flag and enable further interrupts to be generated if any
of the event flags are set to 1.
Figure 8-22. ECAP Interrupt Forcing Register (ECFRC)
13 12
Reserved
R-0
5 4
CTROVF CEVT4
R/W-0 R/W-0
Value Description
0 Any writes to these bit(s) must always have a value of 0.
Force Counter Equal Compare Interrupt
0 No effect. Always reads back a 0.
1 Writing a 1 sets the CTR=CMP flag bit.
Force Counter Equal Period Interrupt
0 No effect. Always reads back a 0.
1 Writing a 1 sets the CTR=PRD flag bit.
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Capture Module - Control and Status Registers
11 10
3 2
CETV3 CETV2
R/W-0 R/W-0
C28 Enhanced Capture (eCAP) Module
9 8
1 0
CETV1 reserved
R/W-0 R-0
845