Interrupt 0-31 Clear Pending (Unpend0) Register; Interrupt 32-63 Clear Pending (Unpend1) Register; Interrupt 0-31 Interrupt Clear Pending (Unpend0) Register Field Descriptions; Interrupt 32-63 Clear Pending (Unpend1) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

www.ti.com
25.5.16 Interrupt 0-31 Clear Pending (UNPEND0) Register, offset 0x280
The Interrupt 0-31 Clear Pending (UNPEND0) register shows which interrupts are pending and removes
the pending state from interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See
the Cortex-M3 Processor chapter for interrupt assignments.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-26. Interrupt 0-31 Interrupt Clear Pending (UNPEND0) Register Field Descriptions
Bit Field
31-0 INT
25.5.17 Interrupt 32-63 Clear Pending (UNPEND1) Register, offset 0x284
The Interrupt 32-63 Clear Pending (UNPEND1) register shows which interrupts are pending and removes
the pending state from interrupts. Bit 0 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. See
the Cortex-M3 Processor chapter for interrupt assignments.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-27. Interrupt 32-63 Clear Pending (UNPEND1) Register Field Descriptions
Bit Field
31-0 INT
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
Figure 25-20. Interrupt 0-31 Clear Pending (UNPEND0) Register
Value Description
Interrupt Clear Pending
0 On a read, indicates that the interrupt is not pending. On a write, no effect.
1 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in
the PEND0 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the active
state of the corresponding interrupt.
Figure 25-21. Interrupt 32-63 Clear Pending (UNPEND1) Register
Value Description
Interrupt Clear Pending
0 On a read, indicates that the interrupt is not pending. On a write, no effect.
1 On a read, indicates that the interrupt is pending. On a write, clears the corresponding INT[n] bit in
the PEND1 register, so that interrupt [n] is no longer pending. Setting a bit does not affect the
active state of the corresponding interrupt
Copyright © 2012–2019, Texas Instruments Incorporated
INT
R/W-0
INT
R/W-0
NVIC Register Descriptions
0
0
1657
Cortex-M3 Peripherals