Speed Of Transactions; Example Schematic For Muxed Host-Bus 16 Mode - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Figure 17-7. Example Schematic for Muxed Host-Bus 16 Mode
EPI_16_BUS
U2
A[0:15]
5
A0
A0 I/O0
4
A1
A1 I/O1
3
A2
A2 I/O2
2
A3
A3 I/O3
1
A4
A4 I/O4
44
A5
A5 I/O5
43
A6
A6 I/O6
42
A7
A7 I/O7
27
A8
A8 I/O8
26
A9
A9 I/O9
25
A10
A10 I/O10
A11 24
A11 I/O11
23
A12
A12 I/O12
22
A13
A13 I/O13
21
A14
A14 I/O14
20
A15
A15 I/O15
EPI16 19
A16
18
EPI17
A17
NC
+3.3V
WE
11
VCC
33
VCC
OE
12
VSS BHE
34
VSS BLE
GND
CY62147

17.7.2 Speed of Transactions

The COUNT0 field in the EPIBAUD register must be configured to set the main transaction rate based on
what the slave device can support (including wiring considerations). The main control transitions are
normally ½ the baud rate (COUNT0 = 1) because the EPI block forces data vs. control to change on
alternating clocks. When using dual chip selects, each chip select can access the bus using differing baud
rates by setting the CSBAUD bit in the EPIHBnCFG2 register. In this case, the COUNT0 field controls the
CS0 transactions, and the COUNT1 field controls the CS1 transactions. When using quad chip select
mode, the COUNT0 bit field of the EPIBAUD2 register controls the baud rate of CS2 and the COUNT1 bit
field is programmed to control the baud rate of CS3.
SPRUHE8E – October 2012 – Revised November 2019
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EPI_16_BUS
47
EPI0
1D1
46
EPI1
1D2
44
EPI2
1D3
43
EPI3
1D4
41
EPI4
1D5
40
EPI5
1D6
38
EPI6
1D7
37
EPI7
1D8
36
EPI8
2D1
35
EPI9
2D2
33
EPI10
2D3
32
EPI11
2D4
30
EPI12
2D5
29
EPI13
2D6
27
EPI14
2D7
26
EPI15
2D8
25
EPI30
2LE
48
1LE
1
1OE
24
2OE
+3.3V
7
VCC
18
VCC
31
VCC
42
VCC
GND
74X16373
EPI_16_BUS
7
EPI0
8
EPI1
9
EPI2
10
EPI3
13
EPI4
14
EPI5
15
EPI6
16
EPI7
29
EPI8
30
EPI9
31
EPI10
32 EPI11
35
EPI12
36
EPI13
37
EPI14
38
EPI15
28
17
EPI29
6
EPI26
CE
41
EPI28
40
EPI25
39
EPI24
Copyright © 2012–2019, Texas Instruments Incorporated
U1
2
A0
1Q1
3
A1
1Q2
5
A2
1Q3
6
A3
1Q4
8
A4
1Q5
9
A5
1Q6
11
A6
1Q7
12
A7
1Q8
13
A8
2Q1
14
A9
2Q2
16
A10
2Q3
17
A11
2Q4
19
A12
2Q5
20
A13
2Q6
22
A14
2Q7
23
A15
2Q8
4
GND
10
GND
15
GND
21
GND
28
GND
34
GND
39
GND
45
GND
GND
EPI_16_BUS
A[0:15]
25
A0
24
A1
23
A2
22
A3
21
A4
20
A5
19
A6
18
A7
8
A8
7
A9
6
A10
A11 5
4
A12
3
A13
2
A14
1
A15
EPI16 48
17
EPI17
16
EPI18
9
10
12
13
14
15
47
SST39VF800A
Host Bus Mode
A[0:15]
U3
29
EPI0
A0 DQ0
31
EPI1
A1 DQ1
33
EPI2
A2 DQ2
35
EPI3
A3 DQ3
38
EPI4
A4 DQ4
40
EPI5
A5 DQ5
42
EPI6
A6 DQ6
44
EPI7
A7 DQ7
30
EPI8
A8 DQ8
32
EPI9
A9 DQ9
34
EPI10
A10 DQ10
36 EPI11
A11 DQ11
39
EPI12
A12 DQ12
41
EPI13
A13 DQ13
43
EPI14
A14 DQ14
45
EPI15
A15 DQ15
A16
A17
A18
11
EPI29
WE
28
EPI28
OE
26
EPI27
CE
NC
+3.3V
NC
37
NC VDD
NC
NC
46
NC VSS
27
NC VSS
GND
External Peripheral Interface (EPI)
EPI_16_BUS
1247