Control Register (Control); Control Register (Control) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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11.8.7 Control Register (CONTROL) — EALLOW Protected
The control register (CONTROL) is shown in
15 14
Reserved OVRFLG
R-0 R-0
7 6
ERRCLR Reserved
R0/S-0
LEGEND: R0/S = Read 0/Set; R = Read only; -n = value after reset
Bit Field
15 Reserved
14 OVRFLG
13 RUNSTS
12 BURSTSTS
11 TRANSFERSTS
10-9 Reserved
8 PERINTFLG
7 ERRCLR
6-5 Reserved
SPRUHE8E – October 2012 – Revised November 2019
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Figure 11-14. Control Register (CONTROL)
13 12
RUNSTS BURSTSTS
R-0 R-0
5 4
PERINTCLR
R-0 R0/S-0
Table 11-9. Control Register (CONTROL) Field Descriptions
Value Description
Reserved
Overflow Flag Bit: This bit indicates if a peripheral interrupt event trigger is received from the
selected peripheral and the PERINTFLG is already set.
0 No overflow event
1 Overflow event
The ERRCLR bit can be used to clear the state of this bit to 0. The OVRFLG bit is not affected
by the PERINTFRC event.
Run Status Bit: This bit is set to 1 when the RUN bit is written to with a 1. This indicates the DMA
channel is now ready to process peripheral interrupt event triggers. This bit is cleared to 0 when
TRANSFER_COUNT reaches zero and CONTINUOUS mode bit is set to 0. This bit is also
cleared to 0 when either the HARDRESET bit, the SOFTRESET bit, or the HALT bit is activated.
0 Chanel is disabled.
1 Channel is enabled.
Burst Status Bit: This bit is set to 1 when a DMA burst transfer begins and the BURST_COUNT
is initialized with the BURST_SIZE. This bit is cleared to zero when BURST_COUNT reaches
zero. This bit is also cleared to 0 when either the HARDRESET or the SOFTRESET bit is
activated.
0 No burst activity
1 The DMA is currently servicing or suspending a burst transfer from this channel.
Transfer Status Bit: This bit is set to 1 when a DMA transfer begins and the address registers are
copied to the shadow set and the TRANSFER_COUNT is initialized with the TRANSFER_SIZE.
This bit is cleared to zero when TRANSFER_COUNT reaches zero. This bit is also cleared to 0
when either the HARDRESET or the SOFTRESET bit is activated.
0 No transfer activity
1 The channel is currently in the middle of a transfer regardless of whether a burst of data is
actively being transferred or not.
Reserved
Peripheral Interrupt Trigger Flag Bit: This bit indicates if a peripheral interrupt event trigger has
occurred. This flag is automatically cleared when the first burst transfer begins.
0 No interrupt event trigger
1 Interrupt event trigger
The PERINTFRC bit can be used to set the state of this bit to 1 and force a software DMA event.
The PERINTCLR bit can be used to clear the state of this bit to 0.
0 Error Clear Bit: Writing a 1 to this bit will clear any latched sync error event and clear the
SYNCERR bit. This bit will also clear the OVRFLG bit. This bit would normally be used when
initializing the DMA for the first time or if an overflow condition is detected. If an ADCSYNC error
event or overflow event occurs at the same time as writing to this bit, the ADC or overrun has
priority and the SYNCERR or OVRFLG bit is set.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
Figure 11-14 and described in
11
TRANSFERSTS
R-0
3
PERINTFRC SOFTRESET
R0/S-0 R0/S-0
C28 Direct Memory Access (DMA) Module
Register Descriptions
Table 11-9.
10 9
Reserved PERINTFLG
R-0
2 1
HALT
R0/S-0
8
R-0
0
RUN
R0/S-0
971