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5.1.1.3
MSG RAM
The third type of shared RAMs are called "message RAM" memories (MSG RAMs). There are only two
such memory blocks in these devices, specifically used for inter-processor communication (IPC) between
the two CPUs. Hence, these are also called as IPC RAMs. The message RAMs will have only CPU and
DMA read/write access from one side (M3 or C28), and CPU/DMA read from the other side. For
MTOCMSGRAM, M3 CPU and uDMA will have read and write accesses, whereas C28 CPU and DMA will
have only read access. Similarly for CTOMMSGRAM, C28 CPU and DMA will have read and write
accesses, whereas M3 CPU and µDMA will have only read access. MSG RAMs have protection for
DMA/µDMA writes which can be enabled/disabled by configuring specific bits in MSGRAMCR registers,
allocated to each subsystem.
5.1.1.4
Access Arbitration
For a shared RAM, multiple accesses from different masters or the same masters (in the case of C28x
CPU) can come at a given time. The maximum number of accesses to any Sx RAM at any given time
depends on the type of shared RAM. To service one out of multiple accesses at a given time, an
arbitration scheme needs to be followed. On Concerto devices the arbitration scheme used is a mix of
round-robin and fixed priority. Arbitration between individual masters is done based on the round-robin
scheme whereas arbitration between different accesses from the C28x CPU is done based on fixed
priority. The round-robin scheme ensures that access from an individual master is not pending beyond a
fixed number of cycles in any scenario.
Accesses from following masters are arbitrated in round-robin fashion.
•
M3 CPU Access (RD/WR)
•
M3 uDMA Access (RD/WR)
•
C28 CPU Aceess (All type of accesses)
•
C28 DMA Access (RD/WR)
The following access from C28x CPU are arbitrated as per fixed priority.
•
C28x-CPU Data Write — highest priority
•
C28x-CPU Data Read
•
C28x-CPU Fetch/Program Read — lowest priority
Even though the C28x-CPU is capable of throwing three different accesses simultaneously, in round-robin
scheme it's given only one slot.
Note: There are also some exception to round robin scheme due to which in some cases two access from
one master could get finished before allowing the access from other masters.
Following are some example which illustrate how the accesses from different masters get arbitrated on
this device in different scenario.
Cycle
Cycle #1
Cycle#2
Cycle #3
Cycle #4
Cycle #5
Cycle
Cycle #1
Cycle #2
SPRUHE8E – October 2012 – Revised November 2019
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Table 5-2. Simple Round Robin
Accesses
M3 Access/uDMA Access/C28x
Access/DMA Access
No Access
No Access
uDMA Access
No Access
Table 5-3. Extra Wait State
Accesses
Master1 Access
Master2 Access
Copyright © 2012–2019, Texas Instruments Incorporated
RAM Control Module
Access Granted
M3 Access
uDMA Access
C28x Access
DMA Access
uDMA Access
Access Granted
Master1 Access
Idle
Internal Memory
465
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