Enhanced Spi Module Overview; Spi Cpu Interface - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Enhanced SPI Module Overview

12.1 Enhanced SPI Module Overview

shows the SPI CPU interfaces.

The SPI module features include:

SPISOMI: SPI slave-output/master-input pin

SPISIMO: SPI slave-input/master-output pin

SPISTE: SPI slave transmit-enable pin

SPICLK: SPI serial-clock pin

NOTE: All four pins can be used as GPIO, if the SPI module is not used.

Two operational modes: master and slave

Baud rate: 125 different programmable rates. The maximum baud rate that can be employed is limited

by the maximum speed of the I/O buffers used on the SPI pins. See the device-specific data sheet for

more details.

Data word length: one to sixteen data bits

Four clocking schemes (controlled by clock polarity and clock phase bits) include:

– Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

– Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

– Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the

rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

Simultaneous receive and transmit operation (transmit function can be disabled in software)

Transmitter and receiver operations are accomplished through either interrupt- driven or polled

C28 Serial Peripheral Interface (SPI)

Figure 12-1. SPI CPU Interface

SPIINT/RXINT

SPRUHE8E – October 2012 – Revised November 2019

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