Error Handling In Different Scenarios - Texas Instruments Concerto F28M36 Series Technical Reference Manual

RAM Control Module
Access Type Error Found In
M3/uDMA Byte Write (R- Data read from memory
M-W)
M3/uDMA Byte Write (R- Data read from memory
M-W)
Reads Data read from memory
Reads Data read from memory
Reads Address
Notes: In case of uncorrectable error duing fetch on C28x CPU, there is possibility of getting ITRAP
before NMI, since garbage instructions enters into C28x pipeline before NMI gets generated.
During debug accesses (RD/WR) correctable as well as uncorrectable errors are masked.
5.1.1.8 Application Test Hooks for Error Detection and Correction
Since error detection and correction logic is part of safety critical logic, safety applications may need to
ensure that the logic is working fine always (during run time also). To enable this, a RAMTEST mode is
provided. When "RAMTEST" mode is set (ECCPARTEST=1), the ECC/parity logic gets bypassed. For
example, while writing the data, only data bit's will be written into memoy not the ECC/parity bits for data
and address. Using this feature an ECC/parity error could be injected into data. Also, the ECC/parity bits
for each address location are memory mapped in separate memory locations, accessible directly by the
CPU. The memory mapped ECC or parity bits can also be changed by the software. During read back, the
ECC / parity logic will detect an error thereby confirming to the application code that ECC/parity logic
works fine. If not then application should consider this as an error condition and handle it accordingly.
Notes: The memory map for ECC/parity bits is accessible only when the RAMTEST mode is selected
(ECCPARTEST=1) or else reads to these address locations return '0.'
In RAMTEST mode, all access to memories (data as well as ECC/partiy) should be done as 32-bit access
only.
The following table shows the bit mapping for the ECC/parity bits when they are read in RAMTEST mode
using their respective addresses.
470
Internal Memory
Table 5-6. Error Handling in Different Scenarios
Error Type
Uncorrectable Error
(Parity Error OR Double
bit ECC Error)
Correctable Error
Uncorrectable Error
(Parity Error OR Double
bit ECC Error)
Single data error
Address error
Copyright © 2012–2019, Texas Instruments Incorporated
Status Indication Error Notification
M3/uDMA Write Address NVIC Interrupt for uDMA
Error Register – Indicates access / bus fault for M3
address for which error access
happened
No None
Yes - M3 / uDMA / C28 NMI for C28 CPU access
CPU / C28 DMA Read NMI for C28 DMA access
Address Error Register BUS FAULT for M3 CPU
Data returned to M3 CPU access
/ uDMA or C28 CPU / C28 Interrupt for uDMA access
DMA is incorrect
Yes - M3 / uDMA / C28 Interrupt on error counter
CPU / C28 DMA Read reaching the user
Address Error Register programmable threshold
Increment single error for single errors
counter
Yes - M3 / uDMA / C28 NMI for C28 CPU access
CPU / C28 DMA Read NMI for C28 DMA access
Address Error Register BUS FAULT for M3 CPU
Data returned to M3 CPU access
/ uDMA or C28 CPU / C28 Interrupt for uDMA access
DMA is incorrect
SPRUHE8E – October 2012 – Revised November 2019
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