M3 Uncorrectable Error Force Register (Muefrc); M3 Uncorrectable Error Force Register (Muefrc) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

RAM Control Module Registers
5.2.2.8

M3 Uncorrectable Error Force Register (MUEFRC)

31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-35. M3 Uncorrectable Error Force Register (MUEFRC) Field Descriptions
Bit Field
31-4 Reserved
3 UDMARE
2 M3CPURE
1 UDMAWE
0 M3CPUWE
498
Internal Memory
Figure 5-26. M3 Uncorrectable Error Force Register (MUEFRC)
R-0
Value Description
Reserved
M3 µDMA Uncorrectable Read Error Force .Any reads to this bit will return a 0.
Setting this bit to 1 will set the M3 µDMA uncorrectable read error flag status.
M3 CPU Uncorrectable Read Error Force. Any reads to this bit will return a 0.
Setting this bit to 1 will set the M3 CPU uncorrectable read error flag status.
M3 µDMA Uncorrectable Write Error Force. Any reads to this bit will return a 0.
Setting this bit to 1 will set the M3 µDMA uncorrectable write error flag status.
M3 CPU Uncorrectable Write Error Force. Any reads to this bit will return a 0.
Setting this bit to 1 will set the M3 CPU uncorrectable write error flag status.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
4 3 2
UDMARE M3CPURE
R/W=1-0 R/W=1-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
16
1 0
UDMAWE M3CPUWE
R/W=1-0 R/W=1-0
Submit Documentation Feedback