Signal Description; Signals For System Control And Clocks - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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1.1

Signal Description

Table 1-1 lists the external signals of the system control module and describes the function of each.
The NMI signal is one of the peripheral functions for the PB7_GPIO15 signal, and functions as a GPIO
after reset. PB7_GPIO15 is under commit protection and requires a special process to be configured as
any alternate function or to subsequently return to the GPIO function. The Pin Mux/ Pin Assignment
column in Table 1-1
can be used as an XCLKIN pin to provide a clock source to the CAN and USB modules on this device.
The PF2_GPIO34 pin can be used as XCLKOUT to monitor the PLL output clock when configured for
either the master subsystem or control subsystem as shown in
configuring GPIOs, see the General-Purpose Input/Outputs (GPIOs) chapter.
The remaining signals (fixed) have a fixed pin assignment and function. Please refer to the device data
manual for more details on the pin numbers.
Pin Functional Pin Name(refer
Name to datasheet for
pin numbers)
NMI PB7_GPIO15
XCLKIN PJ7_GPIO63
XCLKOUT PF2_GPIO34
Refer to the data
X1 manual for pin
Refer to the data
X2 manual for pin
Refer to the data
XRS manual for pin
Refer to the data
ARS manual for pin
Refer to the data
TRST manual for pin
Refer to the data
VREG18EN manual for pin
SPRUHE8E – October 2012 – Revised November 2019
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lists the GPIO options for the NMI signal. When the PJ7_GPIO63 pin is configured, it
Table 1-1. Signals for System Control and Clocks
Pin Mux/ Pin Assignment
Peripheral
Mode
4
0 (default)
0
Don't Care
Fixed
no.
Fixed
no.
Fixed
no.
Fixed
no.
Fixed
no.
Fixed
no.
Copyright © 2012–2019, Texas Instruments Incorporated
Table 1-1. For more information on
Alternate Mode Core Select
Select
0 (default) Master (default)
0 (default) Master (default)
15 Master
3 Control
Fixed Fixed
Fixed Fixed
Fixed Fixed
Fixed Fixed
Fixed Fixed
Fixed Fixed
Signal Description
Description
Non-maskable interrupt
External oscillator input. This pin
feeds a clock from an external 3.3-V
oscillator to the internal USB PLL
module and to the CAN peripherals.
External oscillator output. This pin
outputs a clock divided-down from
the internal PLL System Clock. The
divide ratio is defined in the
XPLLCLKCFG register.
On-chip crystal-oscillator input. To
use this oscillator, a quartz crystal or
a ceramic resonator must be
connected across X1 and X2. In this
case, the XCLKIN path must be
disabled by bit 13 in the CLKCTL
register. If this pin is not used, it
must be tied to GND.
On-chip crystal-oscillator output. A
quartz crystal or a ceramic resonator
must be connected across X1 and
X2. If X2 is not used, it must be left
unconnected.
Digital Subsystem Reset (in) and
Watchdog/Power-on Reset (out). In
most applications, it is recommended
that the XRS pin be tied with the
ARS pin.
Analog subsystem Reset (in) and
Power-on Reset (out). In most
applications, it is recommended that
the ARS pin be tied with the XRS
pin.
JTAG test reset with internal
pulldown
Internal 1.8-V VREG Enable/Disable
for VDD18. Pull low to enable the
internal 1.8-V voltage regulator
(VREG18), pull high to disable
VREG18.
System Control and Interrupts
81