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1.8.4.6
Configuring the Low-Speed Peripheral Clock Prescaler
The low-speed peripheral clock prescale (CLOSPCP) registers are used to configure the low-speed
peripheral clocks. See
1.8.4.7
Configuring Device Clock Domains
The CLKCTL register on the control subsystem can be used to choose between the available clock
sources for the Timer 2 clock. TMR2CLK, as shown in
control subsystem.
1.8.5 Clocking Control Semaphore Functionality
PLL configuration (SYSPLLCTL, SYSPLLMULT, SYSPLLSTS) and SYSDIVSEL configuration are only
accessible by the master subsystem by default, but the control subsystem can request access to these
registers which configure the PLL and SYSDIVSEL by using the clocking control semaphore logic. After
the control subsystem is finished with clock configurations, it can return control back to the master
subsystem. To request access to the control clock configuration and to return the control back to the
previous owner of clock configurations, each subsystem is provided with a clock control semaphore
register. This register is called MCLKREQUEST on the master subsystem, and CLKREQUEST on the
control subsystem. Both registers always reflect the same value when both the master subsystem and
control subsystem write to MCLKREQUEST and CCLKREQUEST, respectively, at the same time. Then,
master subsystem writes are given priority.
By default on power-up or reset, the "SEM" bits (bits 1,0) in the MCLKREQUEST and CCLKREQUEST
registers are set to 0,0. When these bits are "0,0" or "1,0" or "1,1" respectively, the master subsystem
owns the clocking control semaphore and can read/write to the clocking control registers. When the
master subsystem owns the clocking control semaphore, all the clocking control registers are READ-
ONLY by the control subsystem.
When SEM bits are set to "0,1" respectively, the control subsystem owns the clocking control semaphore
and can read/write to the clocking control registers. At this time, these registers are READ-ONLY for the
master subsystem.
Registers which can be accessed by the subsystem which owns the clocking control semaphore currently
are: SYSPLLCTL, SYSPLLMULT, SYSPLLSTS, and SYSDIVSEL.
For the master subsystem to own the clocking control registers:
•
The SEM bits (bits 1,0) in the MCLKREQUEST register must be set to "0,0", "1,1" or "1,0" for the
master subsystem to be able to read/write to the clocking control registers.
•
If the SEM bits (bits 1,0) in the MCLKREQUEST register are set to "1,0", the clocking control
semaphore is owned by the master subsystem. The control subsystem cannot gain this semaphore,
and thus cannot gain access to the clocking control registers when the SEM bits are in this state.
•
If the SEM bits (bits 1,0) in the MCLKREQUEST register are set to "0,1", the clocking control
semaphore is owned by the control subsystem and the master subsystem cannot have access to the
clocking control registers at this point. Therefore, it cannot set the SEM bits back to "0,0" or "1,1" or
"1,0". Only the control subsystem can set the SEM bits to "0,0", "1,1" or "1,0" after they are set to "0,1."
If the user is configuring the clocking registers on the master subsystem, it is advised to set the SEM bits
in the MCLKREQUEST register to "1,0" at least until clock setup is completed. This keeps the software
running on the control subsystem from trying to gain access to the clocking registers while the master
subsystem is configuring them.
For the control subsystem to own the clocking control registers:
•
The SEM bits (bits 1,0) in the CCLKKREQUEST register must be set to "0,1" for the control subsystem
to be able to read/write to the clocking control registers.
•
Once the SEM bits are set to "0,1" in the CCLKREQUEST register by the control subsystem or in the
MCLKREQUEST register by the master susbystem, then only the control subsystem will be able to set
the SEM bits back to "0,0", "1,1" or "1,0" to give access back to the master subsystem.
•
If the SEM bits (bits 1,0) in the CCLKREQUEST register are set to "1,0", the clocking control
semaphore is with the master subsystem and the control subsystem cannot have access to the
clocking control registers at this point. It also cannot set the SEM bits to "0,1". Only the master
SPRUHE8E – October 2012 – Revised November 2019
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Figure 1-130
for the CLOSPCP layout.
Copyright © 2012–2019, Texas Instruments Incorporated
Figure
1-13, is the clock source for Timer 2 on the
System Control and Interrupts
Clock Control
135
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