Configuring A Peripheral For Simple Transmit; Channel Control Structure Offsets For Channel 7; Channel Control Word Configuration For Peripheral Transmit Example - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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16.4.3 Configuring a Peripheral for Simple Transmit

This example configures the µDMA controller to transmit a buffer of data to a peripheral. The peripheral
has a transmit FIFO with a trigger level of 4. The example peripheral uses µDMA channel 7.
16.4.3.1 Configure the Channel Attributes
First, configure the channel attributes:
1. Configure bit 7 of the DMA Channel Priority Set (DMAPRIOSET) or DMA Channel Priority Clear
(DMAPRIOCLR) registers to set the channel to high priority or default priority.
2. Set bit 7 of the DMA Channel Primary Alternate Clear (DMAALTCLR) register to select the primary
channel control structure for this transfer.
3. Set bit 7 of the DMA Channel Useburst Clear (DMAUSEBURSTCLR) register to allow the µDMA
controller to respond to single and burst requests.
4. Set bit 7 of the DMA Channel Request Mask Clear (DMAREQMASKCLR) register to allow the µDMA
controller to recognize requests for this channel.
16.4.3.2 Configure the Channel Control Structure
This example transfers 64 bytes from a memory buffer to the peripheral's transmit FIFO register using
µDMA channel 7. The control structure for channel 7 is at offset 0x070 of the channel control table. The
channel control structure for channel 7 is located at the offsets shown in
Control Table Base + 0x070
Control Table Base + 0x074
Control Table Base + 0x078
16.4.3.2.1 Configure the Source and Destination
The source and destination end pointers must be set to the last address for the transfer (inclusive).
Because the peripheral pointer does not change, it simply points to the peripheral's data register.
• Program the source end pointer at offset 0x070 to the address of the source buffer + 0x3F.
• Program the destination end pointer at offset 0x074 to the address of the peripheral's transmit FIFO
register.
The control word at offset 0x078 must be programmed according to
Table 16-10. Channel Control Word Configuration for Peripheral Transmit Example
Field in DMACHCTL
DSTINC
DSTSIZE
SRCINC
SRCSIZE
reserved
ARBSIZE
XFERSIZE
NXTUSEBURST
XFERMODE
SPRUHE8E – October 2012 – Revised November 2019
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Table 16-9. Channel Control Structure Offsets for Channel 7
Offset
Bits
31:30
29:28
27:26
25:24
23:18
17:14
13:4
3
2:0
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Initialization and Configuration
Table 16-9.
Description
Channel 7 Source End Pointer
Channel 7 Destination End Pointer
Channel 7 Control Word
Table 16-10.
Value Description
Destination address does not
3
0 8-bit destination data size
0 8-bit source address increment
0 8-bit source data size
0
2 Arbitrates after 4 transfers
63 Transfer 64 items
0 N/A for this transfer type
1 Use Basic transfer mode
M3 Micro Direct Memory Access ( µDMA)
increment
Reserved
1203