Timer Modes; 16-Bit Timer With Prescaler Configurations - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Functional Description

2.3.2 Timer Modes

This section describes the operation of the various timer modes. When using Timer A and Timer B in
concatenated mode, only the Timer A control and status bits must be used; there is no need to use Timer
B control and status bits. The GPTM is placed into individual mode by writing a value of 0x4 to the GPTM
Configuration (GPTMCFG) register. In the following sections, the variable "n" is used in bit field and
register names to imply either a Timer A function or a Timer B function. The prescaler is only available in
the 16-bit one-shot, periodic, and input edge count timer mode. Throughout this section, the timeout event
in down-count mode is 0x0 and in up-count mode is the value in the GPTM Timer n Match
(GPTMTnMATCH) and the optional GPTM Timer n Prescale Match (GPTMTnPMR) registers.
2.3.2.1 One-Shot/Periodic Timer Mode
The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the
GPTM Timer n Mode (GPTMTnMR) register. The timer is configured to count up or down using the
TnCDIR bit in the GPTMTnMR register.
When software sets the TnEN bit in the GPTM Control (GPTMCTL) register, the timer begins counting up
from 0x0 or down from its preloaded value. Alternatively, if the TnWOT bit is set in the GPTMTnMR
register, once the TnEN bit is set, the timer waits for a trigger to begin counting.
When the timer is counting down and it reaches the timeout event (0x0), the timer reloads its start value
from the GPTMTnILR and the GPTMTnPR registers on the next cycle. When the timer is counting up and
it reaches the timeout event (the value in the GPTMTnILR and the GPTMTnPR registers), the timer
reloads with 0x0. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in
the GPTMCTL register. If configured as a periodic timer, the timer starts counting again on the next cycle.
In periodic, snap-shot mode (TnSNAPS bit in the GPTMTnMR register is set), the actual free-running
value of the timer at the time-out event is loaded into the GPTMTnR register. In this manner, software can
determine the time elapsed from the interrupt assertion to the ISR entry.
In addition to reloading the count value, the GPTM generates interrupts and triggers when it reaches the
time-out event. The GPTM sets the TnTORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register
and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the timeout
interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the TnTOMIS
bit in the GPTM Masked Interrupt Status (GPTMMIS) register. By setting the TnMIE bit in the GPTMTAMR
register, an interrupt can also be generated when the Timer value equals the value loaded into the GPTM
Timer n Match (GPTMTnMATCH) and GPTM Timer n Prescale Match (GPTMTnPMR) registers. This
interrupt has the same status, masking, and clearing functions as the timeout interrupt. The µDMA trigger
is enabled by configuring and enabling the appropriate µDMA channel. See the Micro Direct Memory
Access (µDMA) chapter.
If software updates the GPTMTnILR register while the counter is counting down, the counter loads the
new value on the next clock cycle and continues counting down from the new value. If software updates
the GPTMTnILR register while the counter is counting up, the timeout event is changed on the next cycle
to the new value. If software updates the GPTM Timer n Value (GPTMTnV) register while the counter is
counting up or down, the counter loads the new value on the next clock cycle and continues counting from
the new value. If software updates the GPTMTnMATCHR register while the counter is counting, the
counter loads the new value on the next clock cycle and continues counting from the new value.
If the TnSTALL bit in the GPTMCTL register is set, the timer freezes counting while the processor is
halted by the debugger. The timer resumes counting when the processor resumes execution.
The following table shows a variety of configurations for a 16-bit free-running timer while using the
prescaler. All values assume a 100-MHz clock with Tc=10 ns (clock period).
Prescale
00000000
00000001
00000010
------------
308
M3 General-Purpose Timers
Table 2-3. 16-Bit Timer With Prescaler Configurations
#Clock (Tc)
1
2
3
--
Copyright © 2012–2019, Texas Instruments Incorporated
Max Time
0.6554
1.3107
1.9661
--
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
www.ti.com
Units
mS
mS
mS
--