Compare Control Register (Cmpctl2); Counter-Compare Control Register (Cmpctl2) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Registers
Table 7-37. Counter-Compare Control Register (CMPCTL) Field Descriptions (continued)
Bit Field
3-2 LOADBMODE
1-0 LOADBMODE
15 14
Reserved
R-0
7 6
Reserved SHDWDMODE
R-0 R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-38. Counter-Compare Control Register (CMPCTL2) Field Descriptions
Bit Field
15-14 Reserved
13-12 LOADDSYNC
11-10 LOADCSYNC
9-7 Reserved
6 SHDWDMODE
5 Reserved
4 SHDWCMODE
780
C28 Enhanced Pulse Width Modulator (ePWM) Module
Value Description
Active Counter-Compare B (CMPB) Load From Shadow Select Mode. This bit has no effect in
immediate mode (CMPCTL[SHDWBMODE] = 1).
00 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01 Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10 Load on either CTR = Zero or CTR = PRD
11 Freeze (no loads possible)
Active Counter-Compare A (CMPA) Load From Shadow Select Mode. This bit has no effect in
immediate mode (CMPCTL[SHDWAMODE] = 1).
00 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01 Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10 Load on either CTR = Zero or CTR = PRD
11 Freeze (no loads possible)
Figure 7-88. Compare Control Register (CMPCTL2)
13 12
LOADDSYNC
R/W
5 4
Reserved SHDWCMODE
R-0 R/W
Value Description
0 Reserved
Shadow to Active CMPD Register Load on SYNC event
00 Shadow to Active Load of CMPD occurs according to LOADDMODE
01 Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC
occurs.
10 Shadow to Active Load of CMPD occurs only when a SYNC is received.
11 Reserved
Note: This bit is valid only if CMPCTL2[SHDWDMODE] = 0.
Shadow to Active CMPC Register Load on SYNC event
00 Shadow to Active Load of CMPC occurs according to LOADCMODE
01 Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC
occurs.
10 Shadow to Active Load of CMPC occurs only when a SYNC is received.
11 Reserved
Note: This bit is valid only if CMPCTL2[SHDWCMODE] = 0.
Reserved
Compare D Register operating mode:
0 Shadow mode – operates as a double buffer. All writes via the CPU access Shadow register.
1 Immediate mode – only the Active compare register is used. All writes/reads via the CPU directly
access the Active register for immediate "Compare action".
0 Reserved
Counter-Compare C Register operating mode
0 Shadow mode – operates as a double buffer. All writes via the CPU access Shadow register.
0 Immediate mode – only the Active compare register is used. All writes/reads via the CPU directly
access the Active register for immediate "Compare action".
Copyright © 2012–2019, Texas Instruments Incorporated
11 10
LOADCSYNC
R/W
3 2
LOADDMODE
R/W
SPRUHE8E – October 2012 – Revised November 2019
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9 8
Reserved
R-0
1 0
LOADCMODE
R/W