Plls - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Clock Control

1.8.2 PLLs

There are two PLLs in this device; one used to generate the clocks for the entire device (system PLL) and
the other to generate the fixed 60 MHz clock to the USB module (USB PLL). The clock input source to the
system PLL is OSCCLK and USBPLL is OSCCLK or GPIO_XCLKIN. Both the PLLs are powered down in
the deep sleep mode.
The clocking control and low power mode control for the M3 and C28 subsystems are separate. This
helps retain compatibility to C2000 devices on the C28 subsystem.
The PLL generates output frequency Fout, based on the following relationship with Fref, the input
frequency. SYSPLLMULT also includes a fractional multiplication portion. Fout from the PLL is a 50% duty
cycle clock, so there is no divider required at the output of the PLL in Concerto™ platform devices for
normal operation.
Fout = Fref * SYSPLLMULT
The PLL by itself supports a Fout range of 110-550 MHz, but in Concerto ™devices, the maximum Fout is
300 MHz, and the maximum system clock (PLLSYSCLK) frequency supported is 150 MHz. There is a
default /2 clock divider at the PLL output in addition to SYSDIVSEL and M3SSDIVSEL which generates
PLLSYSCLK.
So,
PLLSYSCLK = Fref * SYSPLLMULT /2 /SYSDIVSEL divider
M3SSCLK = Fref * SYSPLLMULT / 2 / SYSDIVSEL divider / M3SYSDIVSEL divider
The PLL multiplier bit field is a 9 bit field with 7 bits of the SYSPLLMULT register comprising of the integer
multiplier portion (SPLLIMULT) while the remaining 2 bits support the fractional multiplier (SPLLFMULT).
The value of SPLLIMULT = 0 would default to PLLBYPASS mode where Fout = Fref. As an example,
if SPLLIMULT = 36 and SPLLFMULT = 2, it yields a multiplication factor of 36.5.
For a Fref = 4.11 MHz, the Fout = Fref * 36.5 = 150 MHz, which is further divided by /2, to generate a
PLLSYSCLK frequency of 75 MHz.
NOTE:
1. The application must ensure that PLLCR values should be chosen such that Fout is
always within a permissible Fout range, namely between 110 and 550 MHz.
2. The purpose of /2, /4 and /8 dividers (SYSDIVSEL) is to reduce inrush current at power
up.
The SysCtlClockPllConfig () function in the sysctl.c file may be referenced as an example of a proper PLL
initialization sequence. If this function is not used for PLL configuration, then it is recommended to lock the
PLL twice whenever there is a change in the system clocking frequency, per the following sequence:
• Bypass the PLL
• Write the desired PLL multipliers to the SYSPLLMULT[IMULT] and SYSPLLMULT[FMULT] registers
• Poll the SYSPLLMULT[LOCKS] bit to wait for the first PLL lock sequence to complete
• Rewrite at least one of the multipliers (this will re-start the PLL Lock)
• Poll the lock bit again to ensure proper final PLL initialization
• Configure the system clock dividers
– It is recommended to initially program a system divider which is greater than the final divide value
(lower frequency) in the system. This will limit the instantaneous current increase when the PLL is
selected as the clock source and allow the system voltage regulator to stabilize in smaller current
step increments.
• Re-enable the PLL as the system clocking source
• Set the system dividers to the final values
– The final divider can then be programmed after a small delay determined by the system regulator
and decoupling capacitors stabilize
128
System Control and Interrupts
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SPRUHE8E – October 2012 – Revised November 2019
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