Interrupt Select 1 And 2 Register (Intsel1N2) (Address Offset 08H); Interrupt Select 3 And 4 Register (Intsel3N4) (Address Offset 09H); Interrupt Select 5 And 6 Register (Intsel5N6) (Address Offset 0Ah); Interrupt Select 7 And 8 Register (Intsel7N8) (Address Offset 0Bh) - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Analog-to-Digital Converter (ADC)
Table 10-11. ADC Interrupt Overflow Clear Register (ADCINTOVFCLR) Field Descriptions
Bit Field
15-8 Reserved
7-0 ADCINTx
(x = 8 to 1)
NOTE: The following Interrupt Select Registers are EALLOW protected.
Figure 10-23. Interrupt Select 1 And 2 Register (INTSEL1N2) (Address Offset 08h)
15 14
Reserved INT2CONT
R-0 R/W-0
7 6
Reserved INT1CONT
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 10-24. Interrupt Select 3 And 4 Register (INTSEL3N4) (Address Offset 09h)
15 14
Reserved INT4CONT
R-0 R/W-0
7 6
Reserved INT3CONT
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 10-25. Interrupt Select 5 And 6 Register (INTSEL5N6) (Address Offset 0Ah)
15 14
Reserved INT6CONT
R-0 R/W-0
7 6
Reserved INT5CONT
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Figure 10-26. Interrupt Select 7 And 8 Register (INTSEL7N8) (Address Offset 0Bh)
15 14
Reserved INT8CONT
R-0 R/W-0
7 6
Reserved INT7CONT
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
914
Analog Subsystem
Value Description
0 Reserved
ADC Interrupt Overflow Clear Bits.
0 No action.
1 Clears the respective overflow bit in the ADCINTOVF register. If software tries to set this bit on the
same clock cycle that hardware tries to set the overflow bit in the ADCINTOVF register, then
hardware has priority and the ADCINTOVF bit will be set.
13 12
INT2E
R/W-0
5 4
INT1E
R/W-0
13 12
INT4E
R/W-0
5 4
INT3E
R/W-0
13 12
INT6E
R/W-0
5 4
INT5E
R/W-0
13 12
INT8E
R/W-0
5 4
INT7E
R/W-0
Copyright © 2012–2019, Texas Instruments Incorporated
INT2SEL
R/W-0
INT1SEL
R/W-0
INT4SEL
R/W-0
INT3SEL
R/W-0
INT6SEL
R/W-0
INT5SEL
R/W-0
INT8SEL
R/W-0
INT7SEL
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
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