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Register Map
16.4.4.3 Configure the Peripheral Interrupt
An interrupt handler should be configured when using µDMA Ping-Pong mode, it is best to use an
interrupt handler. However, the Ping-Pong mode can be configured without interrupts by polling. The
interrupt handler is triggered after each buffer is complete.
•
Configure and enable an interrupt handler for the peripheral.
16.4.4.4 Enable the µDMA Channel
Now the channel is configured and is ready to start.
Enable the channel by setting bit 8 of the DMA Channel Enable Set (DMAENASET) register.
16.4.4.5 Process Interrupts
The µDMA controller is now configured and enabled for transfer on channel 8. When the peripheral
asserts the µDMA request signal, the µDMA controller makes transfers into buffer A using the primary
channel control structure. When the primary transfer to buffer A is complete, it switches to the alternate
channel control structure and makes transfers into buffer B. At the same time, the primary channel control
word mode field is configured to indicate Stopped, and an interrupt is generated in the peripheral's raw
interrupt status register.
When an interrupt is triggered, the interrupt handler must determine which buffer is complete and process
the data or set a flag that the data must be processed by non-interrupt buffer processing code. Then the
next buffer transfer must be set up.
In the interrupt handler:
•
Read the primary channel control word at offset 0x088 and check the XFERMODE field. If the field is
0, this means buffer A is complete. If buffer A is complete, then:
– Process the newly received data in buffer A or signal the buffer processing code that buffer A has
data available.
– Reprogram the primary channel control word at offset 0x88 according to
•
Read the alternate channel control word at offset 0x288 and check the XFERMODE field. If the field is
0, this means buffer B is complete. If buffer B is complete, then:
– Process the newly received data in buffer B or signal the buffer processing code that buffer B has
data available.
– Reprogram the alternate channel control word at offset 0x288 according to
16.5 Register Map
lists the µDMA channel control structures and registers. The channel control structure shows the layout of
one entry in the channel control table. The channel control table is located in system memory, and the
location is determined by the application, that is, the base address is n/a (not applicable). In the table
below, the offset for the channel control structures is the offset from the entry in the channel control table.
See
Section 16.3.5
located in memory. The µDMA register addresses are given as a hexadecimal increment, relative to the
µDMA base address of 0x400F.F000 (ending address of 0x400F.FFFF). Note that the µDMA module clock
must be enabled before the registers can be programmed. There must be a delay of 3 system clocks after
the µDMA module clock is enabled before any µDMA module registers are accessed.
Offset Name
Name
μDMA Channel Control Structure (Offset from Channel Control Table Base)
0x000
DMASRCENDP
0x004
DMADSTENDP
0x008
DMACHCTL
1206
M3 Micro Direct Memory Access ( µDMA)
and
Table 16-3
for a description of how the entries in the channel control table are
Type
R/W
R/W
R/W
Copyright © 2012–2019, Texas Instruments Incorporated
Table 16-13.
Reset
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-
-
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Table
16-12.
Table
16-12.
Description
DMA Channel Source
Address End Pointer
DMA Channel Destination
Address End Pointer
DMA Channel Control Word
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