Ssipp Register; Ssipp Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

SSI Registers
20.5.2.12 SSIPP Register (Offset = FC0h) [reset = 9h]
SSIPP is shown in
Return to the Summary
SSI Peripheral Properties
31 30
23 22
15 14
7 6
RESERVED
R-0h
Bit Field
31-5 RESERVED
3 FSSHLDFRM
2-1 MODE
0 HSCLK
1474
M3 Synchronous Serial Interface (SSI)
Figure 20-21 and described in
Table.
Figure 20-21. SSIPP Register
29 28
21 20
13 12
5 4
Table 20-15. SSIPP Register Field Descriptions
Type Reset
R 0h
R 1h
R 0h
R 1h
Copyright © 2012–2019, Texas Instruments Incorporated
Table 20-15.
27
RESERVED
R-0h
19
RESERVED
R-0h
11
RESERVED
R-0h
3
FSSHLDFRM
R-1h
Description
Reserved
SSInFss Hold Frame Capability
Value Description
0 Hold Frame capability disabled.SSInFss
1 Hold Frame capability enabled.SSinFss
Reset type: PER.RESET
Mode of Operation Indicates what SSI functionality is
supported.
Value Description
0x0 Legacy SSI mode
Others reserved
Reset type: PER.RESET
High Speed Capability
Value Description
0 High Speed clock capability disabled.
1 High speed clock capability enabled.
Reset type: PER.RESET
SPRUHE8E – October 2012 – Revised November 2019
26 25
18 17
10 9
2 1
MODE
R-0h
Submit Documentation Feedback
www.ti.com
24
16
8
0
HSCLK
R-1h