Master Dma Write Access Violation Address Register (Mmdmawravaddr); Master Cpu Fetch Access Violation Address Register (Mmfavaddr); Master Dma Write Access Violation Address Register (Cmdmawravaddr) Field Descriptions; Master Cpu Fetch Access Violation Address Register (Mmfavaddr) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

RAM Control Module Registers

5.2.2.24 Master DMA Write Access Violation Address Register (MMDMAWRAVADDR)

Figure 5-42. Master DMA Write Access Violation Address Register (MMDMAWRAVADDR)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-51. Master DMA Write Access Violation Address Register (CMDMAWRAVADDR) Field
Bit Field
31-0 MDMAWRAVADDR
Figure 5-43. Master CPU Fetch Access Violation Address Register (MMFAVADDR)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-52. Master CPU Fetch Access Violation Address Register (MMFAVADDR) Field
Bit Field
31-0 MCPUFAVADDR
506
Internal Memory
NMDMAWRAVADDR
R-0
Descriptions
Value Description
Master DMA Write Access Violation Address
This holds the address at which M3 µDMA attempted a write access and the master DMA
write access violation occurred.
MCPUFAVADDR
R-0
Descriptions
Value Description
Master CPU Fetch Access Violation Address
This holds the address at which M3 CPU attempted a code fetch and the master CPU
fetch access violation occurred.
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SPRUHE8E – October 2012 – Revised November 2019
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