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•
Enable all channels or only selected channels for reception (RMCM)
•
Choose which channels are enabled/disabled and masked/unmasked for transmission (XMCM)
•
Specify whether two partitions (32 channels at a time) or eight partitions (128 channels at a time) can
be used (RMCME for reception, XMCME for transmission)
•
Assign blocks of 16 channels to partitions A and B when the 2-partition mode is selected (RPABLK and
RPBBLK for reception, XPABLK and XPBBLK for transmission)
•
Determine which block of 16 channels is currently involved in a data transfer (RCBLK for reception,
XCBLK for transmission)
15.12.8.1 Multichannel Control 1 Register (MCR1)
The multichannel control 1 register (MCR1) is shown in
15
7
6
RPBBLK
RPABLK
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15-84. Multichannel Control 1 Register (MCR1) Field Descriptions
Bit
Field
15-10
Reserved
9
RMCME
SPRUHE8E – October 2012 – Revised November 2019
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Figure 15-75. Multichannel Control 1 Register (MCR1)
Reserved
R-0
5
4
R/W-0
Value
Description
0
Reserved bits (not available for your use). They are read-only bits and return 0s when read.
Receive multichannel partition mode bit. RMCME is only applicable if channels can be individually
enabled or disabled for reception (RMCM = 1).
RMCME determines whether only 32 channels or all 128 channels are to be individually selectable.
0
2-partition mode
Only partitions A and B are used. You can control up to 32 channels in the receive multichannel
selection mode (RMCM = 1).
Assign 16 channels to partition A with the RPABLK bits.
Assign 16 channels to partition B with the RPBBLK bits.
You control the channels with the appropriate receive channel enable registers:
RCERA: Channels in partition A
RCERB: Channels in partition B
1
8-partition mode
All partitions (A through H) are used. You can control up to 128 channels in the receive
multichannel selection mode. You control the channels with the appropriate receive channel enable
registers:
RCERA: Channels 0 through 15
RCERB: Channels 16 through 31
RCERC: Channels 32 through 47
RCERD: Channels 48 through 63
RCERE: Channels 64 through 79
RCERF: Channels 80 through 95
RCERG: Channels 96 through 111
RCERH: Channels 112 through 127
Copyright © 2012–2019, Texas Instruments Incorporated
Figure 15-75
and described in
10
2
RCBLK
R-0
C28 Multichannel Buffered Serial Port (McBSP)
McBSP Registers
Table
15-84.
9
8
RMCME
RPBBLK
R/W-0
R/W-0
1
0
Reserved
RMCM
R-0
R/W-0
1171
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