Non-Master Access Violation Flag Register (Cnmavflg); Non-Master Access Violation Flag Register (Cnmavflg) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

RAM Control Module Registers

5.2.4.14 Non-Master Access Violation Flag Register (CNMAVFLG)

Figure 5-69. Non-Master Access Violation Flag Register (CNMAVFLG)
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-78. Non-Master Access Violation Flag Register (CNMAVFLG) Field Descriptions
Bit Field
31-3 Reserved
2 CPUWRITE
1 DMAWRITE
0 CPUFETCH
528
Internal Memory
Reserved
R-0
Value Description
Reserved
Non-Master CPU Write Access Violation Flag
0 Non-master CPU write access violation did not occur.
1 Non-master CPU write access violation has occurred. The C28x CPU tried to write into an Sx RAM
block for which M3 subsystem is the master.
Once this bit is set, it can be cleared by setting the corresponding error clear bit in the CNMAVCLR
register.
Non-Master DMA Write Access Violation Flag
0 Non-master DMA write access violation did not occur.
1 Non-master DMA write access violation has occurred. The C28x DMA tried to write into an Sx RAM
block for which M3 subsystem is the master. In this case, writes are ignored.
Once this bit is set, it can be cleared by setting the corresponding error clear bit in the CNMAVCLR
register.
Non-Master CPU Fetch Access Violation Flag
0 Non-master CPU fetch access violation did not occur.
1 Non-master CPU fetch access violation has occurred. The C28x CPU tried to fetch code from an Sx
RAM block for which M3 subsystem is the master.
Once this bit is set, it can be cleared by setting the corresponding error clear bit in the CNMAVCLR
register.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
CPUWRITE
R-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
16
1 0
DMAWRITE CPUFETCH
R-0 R-0
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