Master Access Violation Flag Register (Mmavflg); Master Access Violation Flag Register (Mmavflg) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 5-44. Non-Master Access Violation Flag Clear Register (MNMAVCLR) Field Descriptions (continued)
Bit Field
1 DMAWRITE
0 CPUFETCH

5.2.2.18 Master Access Violation Flag Register (MMAVFLG)

31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-45. Master Access Violation Flag Register (MMAVFLG) Field Descriptions
Bit Field
31-3 Reserved
2 CPUWRITE
1 DMAWRITE
0 CPUFETCH
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
Non-Master DMA Write Access Violation Flag
0 Non-master µDMA write access violation did not occur.
1 Non-master µDMA write access violation has occurred. The M3 DMA tried to write into an Sx RAM
block for which C28x subsystem is the master. In this case, writes are ignored.
Non-Master CPU Fetch Access Violation Flag
0 Non-master CPU fetch access violation did not occur.
1 Non-master CPU fetch access violation has occurred. The M3 CPU tried to fetch code from an Sx
RAM block for which C28x subsystem is the master.
Figure 5-36. Master Access Violation Flag Register (MMAVFLG)
Reserved
R-0
Value Description
Reserved
Master CPU Write Access Violation Flag
0 Master CPU write access violation did not occur.
1 Master CPU write access violation has occurred. The M3 CPU tried to write into a RAM Block for
which CPUWRPROT is set to 1.
Once this bit is set, it can be cleared by setting the corresponding error clear bit in the MNMAVCLR
register.
Master DMA Write Access Violation Flag
0 Master DMA write access violation did not occur.
1 Master DMA write access violation has occurred. The M3 µDMA tried to write into a RAM Block for
which DMAWRPROT is set to 1. In this case, writes are ignored.
Once this bit is set, it can be cleared by setting the corresponding error clear bit in the MNMAVCLR
register.
Master CPU Fetch Access Violation Flag
0 Master CPU fetch access violation did not occur.
1 Master CPU fetch access violation has occurred. The M3 CPU tried to fetch code from a RAM
Block for which FETCHPROT is set to 1.
Once this bit is set, it can be cleared by setting the corresponding error clear bit in the MNMAVCLR
register.
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R-0
3 2
CPUWRITE
R-0
RAM Control Module Registers
16
1 0
DMAWRITE CPUFETCH
R-0 R-0
Internal Memory
503