Select Sources To Provide The Receive Frame-Synchronization Signal And The Effect On The Fsr Pin - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Receiver Configuration
Table 15-36. Register Bits Used to Set the Receive Frame Synchronization Mode (continued)
Register Bit
SRGR2 15
SPCR1 15
SPCR1 12-11
Table 15-37. Select Sources to Provide the Receive Frame-Synchronization Signal and the Effect
DLB FSRM
0 0
0 1
0 1
1 0
1126
C28 Multichannel Buffered Serial Port (McBSP)
Name Function
GSYNC Sample rate generator clock synchronization mode
If the sample rate generator creates a frame-synchronization signal
(FSG) that is derived from an external input clock, the GSYNC bit
determines whether FSG is kept synchronized with pulses on the FSR
pin.
GSYNC = 0
GSYNC = 1
DLB Digital loopback mode
DLB = 0
DLB = 1
CLKSTP Clock stop mode
CLKSTP = 0Xb
CLKSTP = 10b
CLKSTP = 11b
on the FSR Pin
Source of Receive Frame
GSYNC Synchronization
0 or 1 An external frame-synchronization signal
enters the McBSP through the FSR pin.
The signal is then inverted as determined
by FSRP before being used as internal
FSR.
0 Internal FSR is driven by the sample rate
generator frame-synchronization signal
(FSG).
1 Internal FSR is driven by the sample rate
generator frame-synchronization signal
(FSG).
0 Internal FSX drives internal FSR.
Copyright © 2012–2019, Texas Instruments Incorporated
No clock synchronization is used: CLKG
oscillates without adjustment, and FSG pulses
every (FPER + 1) CLKG cycles.
Clock synchronization is used. When a pulse is
detected on the FSR pin:
• CLKG is adjusted as necessary so that it is
synchronized with the input clock on the
MCLKR pin.
• FSG pulses FSG only pulses in response
to a pulse on the FSR pin. The frame-
synchronization period defined in FPER is
ignored.
For more details, see Section 15.4.3,
Synchronizing Sample Rate Generator Outputs
to an External Clock.
Digital loopback mode is disabled.
Digital loopback mode is enabled. The receive
signals, including the receive frame-
synchronization signal, are connected internally
through multiplexers to the corresponding
transmit signals.
Clock stop mode disabled; normal clocking for
non-SPI mode.
Clock stop mode enabled without clock delay.
The internal receive clock signal (MCLKR) and
the internal receive frame-synchronization signal
(FSR) are internally connected to their transmit
counterparts, CLKX and FSX.
Clock stop mode enabled with clock delay. The
internal receive clock signal (MCLKR) and the
internal receive frame-synchronization signal
(FSR) are internally connected to their transmit
counterparts, CLKX and FSX.
FSR Pin Status
Input
Output. FSG is inverted as determined by
FSRP before being driven out on the
FSR pin.
Input. The external frame-synchronization
input on the FSR pin is used to
synchronize CLKG and generate FSG
pulses.
High impedance
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Reset
Type Value
R/W 0
R/W 0
R/W 00
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